50G Interlaken MegaCore Function User Guide

ID 683217
Date 9/20/2022

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Document Table of Contents Connecting the Reconfiguration Controller to the IP Core

The Reconfiguration Controller communicates with the 50G Interlaken IP core on two busses:

  • reconfig_to_xcvr (output)
  • reconfig_from_xcvr (input)

Each of these busses connects to the bus of the same name in the 50G Interlaken IP core.

You must also connect the following signals:

  • mgmt_clk_clk: Reconfiguration Controller clock (input)
  • mgmt_rst_reset: Reconfiguration Controller reset (input)
  • reconfig_busy: Reconfiguration Controller busy indication (output)
Figure 6. Typical Connection of Reconfiguration Controller to 50G Interlaken IP Core

Intel® recommends that you set the Reconfiguration Controller input clock frequency in the range of 100 MHz to 125 MHz. Refer to the Intel® Transceiver PHY IP Core User Guide for frequency range requirements specific to the device family.

The Reconfiguration Controller reset input should be asserted high during power up and remain asserted until its clock input becomes stable with the mgmt_clk_locked signal indicating a locked condition of the clock. Upon power up, the Reconfiguration Controller asserts reconfig_busy output high. The reconfig_busy signal remains asserted until the Reconfiguration Controller completes the configuration of all transceivers.

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