50G Interlaken MegaCore Function User Guide

ID 683217
Date 9/20/2022

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4.3.3. IP Core Reset Sequence with the Reconfiguration Controller

If your 50G Interlaken IP core targets an Arria V device or a Stratix V device, you must connect the 50G Interlaken IP core to an Intel® Reconfiguration Controller. At power up, the Reconfiguration Controller configures the transceivers. After power up, upon completion of the transceiver configuration process, the Reconfiguration Controller returns control of the reset to your application. You must wait until the Reconfiguration Controller completes configuration of the transceivers before you assert the reset_n signal.

The Reconfiguration Controller indicates the end of the configuration cycle by deasserting the reconfig_busy signal. After reconfig_busy is deasserted, you can assert reset_n. Intel® recommends that you hold the reset_n signal low for at least the duration of two mm_clk cycles, to ensure the reset sequence proceeds correctly.

Figure 10. Reset Sequence With the Reconfiguration Controller Indicates when you can safely assert the reset_n signal of the 50G Interlaken IP core.

You must wait at least 2(CNTR_BITS + 3) mm_clk cycles after the mgmt_clk locks before you deassert the mgmt_rst_reset input signal to the reconfiguration controller.