50G Interlaken MegaCore Function User Guide

ID 683217
Date 9/20/2022
Public

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5.6.3. Intel® Arria® 10 Transceiver Reconfiguration Interface Signals

The 50G Interlaken IP core Intel® Arria® 10 transceiver reconfiguration interface allows you to communicate with Intel® Arria® 10 hard PCS registers. This interface is available only in variations that target an Intel® Arria® 10 device. You use this interface to reconfigure the transceiver and to take advantage of built-in transceiver features that the 50G Interlaken IP Core supports for IP core testing. The interface allows you to address a single register in a single transceiver channel at one time.

The Intel® Arria® 10 transceiver reconfiguration interface is a typical 32-bit memory-mapped register port. It complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications.

Table 18.   50G Interlaken IP Core Intel® Arria® 10 Transceiver Reconfiguration Interface Signals

Signal Name

Direction

Width (Bits)

Description

reconfig_clk

Input

1

Intel® Arria® 10 transceiver reconfiguration interface clock.

reconfig_reset

Input

1

Assert this signal to reset the Intel® Arria® 10 transceiver reconfiguration interface.

reconfig_read

Input

1

Read access to the Intel® Arria® 10 hard PCS registers.

reconfig_write

Input

1

Write access to the Intel® Arria® 10 hard PCS registers.

reconfig_address

Input

13

Address to access the hard PCS registers. This signal holds both the hard PCS register offset and the transceiver channel being addressed, in the following fields:

  • [9:0]: register offset in the hard PCS
  • [12:10]: Interlaken lane number

reconfig_readdata

Output

32

After user logic asserts the reconfig_read signal, when the IP core deasserts the reconfig_waitrequest signal, reconfig_readdata holds valid read data.

reconfig_waitrequest

Output

1

Busy signal for reconfig_readdata.

reconfig_writedata

Input

32

When reconfig_write is high, reconfig_writedata holds valid write data.