50G Interlaken MegaCore Function User Guide

ID 683217
Date 9/20/2022
Public

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5.5. 50G Interlaken IP Core Management Interface

The 50G Interlaken IP core management interface allows you to communicate with IP core internal status and control registers. This interface manages the PMA (resets and serial loopback controls) and PCS control and status registers. This interface does not provide access to the hard PCS registers on the device.

The management interface is a typical 32-bit memory-mapped register port. It complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications.

Table 15.   50G Interlaken IP Core Management Interface Signals

Signal Name

Direction

Width (Bits)

Description

50G Interlaken IP Core Management Interface Signals

mm_clk

Input

1

Management clock. Clocks the register accesses. It is also used for clock rate monitoring and some analog calibration procedures. You must run this clock at a frequency in the range of 100 MHz–125 MHz.

mm_clk_locked

Input

1

Assert this signal to indicate that mm_clk is stable.

The IP core responds to this signal in the same way it responds to the reset_n signal: loss of lock restarts the reset sequence.

Intel® recommends that you tie this signal high and not rely on its functionality. It is expected to be deprecated in the near future.

mm_read

Input

1

Read access to the register ports.

mm_write

Input

1

Write access to the register ports.

mm_addr

Input

16

Address to access the register ports.

mm_rdata

Output

32

When mm_rdata_valid is high, mm_rdata holds valid read data.

mm_rdata_valid

Output

1

Valid signal for mm_rdata.

mm_wdata

Input

32

When mm_write is high, mm_wdata holds valid write data.

If you do not use the management interface, drive the management inputs as follows:

  • mm_clk must connect to a stable clock. However, the clock signal need not be of unusually high quality.
  • mm_clk_locked must be tied to zero.
  • mm_read and mm_write must be tied to zero.

If you use the management interface, drive the control lines as shown in the examples and observing the following constraints:

  • During a write operation, you must maintain the the mm_write signal asserted for at least two clock cycles. Back-to-back writes must be separated by at least one clock cycle.
  • During a read operation, you must maintain the mm_read signal asserted for at least two clock cycles. Back-to-back reads must be separated by at least one clock cycle.
Figure 18.  50G Interlaken IP Core Management Interface Write Operation

Shows the timing requirements for a write operation on the 50G Interlaken IP core management interface.

Figure 19.  50G Interlaken IP Core Management Interface Read Operation

Shows the timing requirements for a read operation on the 50G Interlaken IP core management interface. The IP core asserts the mm_rdata_valid signal one cycle after the mm_read signal is asserted.