50G Interlaken MegaCore Function User Guide

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ID 683217
Date 9/20/2022
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Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. Getting Started With the 50G Interlaken IP Core 3. 50G Interlaken IP Core Parameter Settings 4. Functional Description 5. 50G Interlaken IP core Signals 6. 50G Interlaken IP Core Register Map 7. 50G Interlaken IP Core Test Features 8. Advanced Parameter Settings 9. Out-of-Band Flow Control in the 50G Interlaken IP core 10. 50G Interlaken IP core User Guide Archives 11. Document Revision History for 50G Interlaken User Guide A. Performance and Fmax Requirements for 40G Ethernet Traffic
1. About This IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grade Support 1.6. Release Information
1.1. Features x
1.1.1. IP Core Supported Combinations of Number of Lanes and Data Rate 1.1.2. IP Core Raw Aggregate Bandwidth
2. Getting Started With the 50G Interlaken IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 50G Interlaken IP Core Parameters and Options 2.3. Files Generated for Arria V GZ and Stratix V Variations 2.4. Files Generated for Intel® Arria® 10 Variations 2.5. Simulating the 50G Interlaken IP Core 2.6. Integrating Your IP Core in Your Design 2.7. Compiling the Full Design and Programming the FPGA 2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. Transceiver Logical Channel Numbering 2.6.3. Adding the Reconfiguration Controller 2.6.4. Adding the External PLL
2.6.3. Adding the Reconfiguration Controller x
2.6.3.1. Generating the Reconfiguration Controller 2.6.3.2. Connecting the Reconfiguration Controller to the IP Core
3. 50G Interlaken IP Core Parameter Settings x
3.1. Meta Frame Length in Words 3.2. Enable Native PHY Debug Master Endpoint (NPDME) 3.3. Transceiver Reference Clock Frequency 3.4. Number of Calendar Pages 3.5. TX Scrambler Seed 3.6. Transfer Mode Selection
4. Functional Description x
4.1. Interfaces Overview 4.2. High Level Block Diagram 4.3. Clocking and Reset Structure for IP Core 4.4. Interleaved and Packet Modes 4.5. 50G Interlaken IP Core Transmit Path 4.6. 50G Interlaken IP Core Receive Path
4.1. Interfaces Overview x
4.1.1. Application Interface 4.1.2. Interlaken Interface 4.1.3. Out‑of‑Band Flow Control Interface 4.1.4. Management Interface 4.1.5. Transceiver Control Interfaces
4.1.5. Transceiver Control Interfaces x
4.1.5.1. Transceiver Reconfiguration Controller Interface 4.1.5.2. Intel® Arria® 10 External PLL Interface 4.1.5.3. Intel® Arria® 10 Transceiver Reconfiguration Interface
4.3. Clocking and Reset Structure for IP Core x
4.3.1. 50G Interlaken IP Core Clock Signals 4.3.2. IP Core Reset 4.3.3. IP Core Reset Sequence with the Reconfiguration Controller
4.5. 50G Interlaken IP Core Transmit Path x
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples 4.5.2. 50G Interlaken IP Core In-Band Calendar Bits on Transmit Side 4.5.3. 50G Interlaken IP Core Transmit Path Blocks
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples x
4.5.1.1. 50G Interlaken IP Core Interleaved Mode (Segmented Mode) Example 4.5.1.2. 50G Interlaken IP Core Packet Mode Operation Example 4.5.1.3. 50G Interlaken IP Core Back-Pressured Packet Transfer Example
4.5.3. 50G Interlaken IP Core Transmit Path Blocks x
4.5.3.1. 50G Interlaken IP Core TX Transmit Buffer 4.5.3.2. 50G Interlaken IP Core TX MAC 4.5.3.3. 50G Interlaken IP Core TX PCS 4.5.3.4. 50G Interlaken IP Core TX PMA
4.6. 50G Interlaken IP Core Receive Path x
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples 4.6.2. 50G Interlaken IP Core RX Errored Packet Handling 4.6.3. In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface 4.6.4. 50G Interlaken IP Core Receive Path Blocks
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples x
4.6.1.1. 50G Interlaken IP Core Receiver Side Example
4.6.2. 50G Interlaken IP Core RX Errored Packet Handling x
4.6.2.1. 50G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
4.6.4. 50G Interlaken IP Core Receive Path Blocks x
4.6.4.1. 50G Interlaken IP Core RX PMA 4.6.4.2. 50G Interlaken IP Core RX PCS 4.6.4.3. 50G Interlaken IP Core RX MAC 4.6.4.4. 50G Interlaken IP Core RX Regroup Block
5. 50G Interlaken IP core Signals x
5.1. 50G Interlaken IP Core Clock Interface Signals 5.2. 50G Interlaken IP Core Reset Interface Signals 5.3. 50G Interlaken IP Core User Data Transfer Interface Signals 5.4. 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals 5.5. 50G Interlaken IP Core Management Interface 5.6. Device Dependent Signals
5.6. Device Dependent Signals x
5.6.1. Transceiver Reconfiguration Controller Interface Signals 5.6.2. Intel® Arria® 10 External PLL Interface Signals 5.6.3. Intel® Arria® 10 Transceiver Reconfiguration Interface Signals
7. 50G Interlaken IP Core Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode 7.3. PRBS Generation and Validation 7.4. CRC32 Error Injection
7.3. PRBS Generation and Validation x
7.3.1. Setting up PRBS Mode in Arria V and Stratix V Devices 7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices
8. Advanced Parameter Settings x
8.1. Hidden Parameters 8.2. Modifying Hidden Parameter Values
8.1. Hidden Parameters x
8.1.1. Required User Clock Frequency 8.1.2. Counter Reset Bits 8.1.3. Include Temp Sense 8.1.4. RXFIFO Address Width 8.1.5. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping) 8.1.6. Use ATX or CMU PLL 8.1.7. Lane Profile
9. Out-of-Band Flow Control in the 50G Interlaken IP core x
9.1. Out-of-Band Flow Control Block Clocks 9.2. TX Out‑of‑Band Flow Control Signals 9.3. RX Out-of-Band Flow Control Signals
1. About This IP Core
2. Getting Started With the 50G Interlaken IP Core
3. 50G Interlaken IP Core Parameter Settings
4. Functional Description
5. 50G Interlaken IP core Signals
6. 50G Interlaken IP Core Register Map
7. 50G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 50G Interlaken IP core
10. 50G Interlaken IP core User Guide Archives
11. Document Revision History for 50G Interlaken User Guide
A. Performance and Fmax Requirements for 40G Ethernet Traffic

11. Document Revision History for 50G Interlaken User Guide

Version Intel® Quartus® Prime Version Changes
2022.09.20 16.0 Corrected the description of PCS_BASE register.
2019.03.15 16.0 Clarified the file location of the out-of-band flow control blocks in section Out-of-Band Flow Control in the 50G Interlaken MegaCore Function.
2018.03.05 16.0 Corrected bit range of reconfig_address signal in Arria 10 Transceiver Reconfiguration Interface Signals section.
2016.05.02 16.0
  • Added a new topic titled Creating a SignalTap II Debug File to Match Your Design Hierarchy.
  • Removed callouts to set_global_assignment -name DISABLE_EMBEDDED_TIMING_CONSTRAINT ON .
  • Removed the chapter Arria 10 Hardware Example Design and 50G Interlaken IP Core Testbench, instead refer to the 50G Interlaken Example Design User Guide.
2015.11.02 15.1
  • Updated for new Quartus Prime software v15.1 release.
  • Added new Enable Native XCVR PHY ADME parameter for Arria 10 variations.
  • Updated with change in process to generate legacy testbench.
  • Added new Arria 10 hardware example design.
  • Updated generated directory structure for non-Arria 10 variations and location of testbench files for all variations.
  • Corrected descriptions of TX out-of-band flow control interface signals fc_clk, fc_data, and fc_sync to indicate they are intended to connect to an upstream RX out-of-band block rather than a downstream block.
  • Corrected 50G Interlaken IP Core Transceiver Initialization Sequence figure. Corrected descriptions of use of reset_n signal to indicate user must assert (low) and deassert (raise) the signal to initiate the reset sequence.
2015.05.04 15.0
  • Added new TX scrambler seed parameter. Previously this parameter was hidden (SCRAM_CONST) and unavailable for Arria 10 devices. In the IP core version 15.0 and later, you must modify the scrambler seed from the parameter editor.
  • Improved description of itx_ifc_err output signal.
  • Improved description of itx_hungry output signal.
  • Updated filenames for hidden parameter editing to include the filenames for Arria 10 variations.
2014.12.15 14.1
  • Updated release-specific information for the software release v14.1, including new resource utilization numbers and new Arria 10 speed grade notation and information. Resource utilization numbers improved by 20% in the v14.0 release.
  • Updated for new Quartus II IP Catalog, which replaces the MegaWizard Plug-In Manager starting in the Quartus II software v14.0. Changes are located primarily in Getting Started with the 50G Interlaken IP Core chapter. Reordered the chapter to accommodate the new descriptions.
  • Corrected instructions to connect the external TX PLL to include the tx_cal_busy signal, and added example figure to illustrate the required connections between the IP core and an ATX PLL. Changes are located in Adding the External PLL section. .
  • Added information about the required wait from reset to successful register access in IP Core Reset section. .
  • Corrected width of reconfig_waitrequest signal to one bit. This signal has been a single bit in all versions that support Arria 10 devices, starting with the IP core version 13.1 Arria 10 Edition.
  • Added information about turning on and off loopback mode in two new sections, External Loopback Mode and Internal Serial Loopback Mode, in IP Core Test Features chapter.
  • Clarified that Counter Reset Bits is the CNTR_BITS advanced parameter, in Counter Reset Bits section.
  • Added new advanced parameter, TX_USR_CLK_MHZ, that specifies the required frequency of the two input clocks tx_usr_clk and rx_usr_clk. Added new section in Advanced Parameter Settings chapter, and clarified required frequencies in 50G Interlaken IP Core Clock Interface Signals section. This advanced parameter is included in the IP core version 14.0 and later.
  • Corrected instructions to modify the USE_ATX advanced parameter by moving the parameter to the correct list in Modifying Hidden Parameter Values section.
  • Clarified that the testbench and example design are generated only if you specify the IP core synthesis and simulation models are in Verilog HDL. The IP core does not support VHDL models, despite the fact that in the IP core v14.0 and later, the parameter editor appears to offer that option.
  • Fixed assorted typos and formatting issues.

December 2013

13.1 Arria 10 Edition (2013.12. 02)

  • Added preliminary support for Arria 10 devices.
  • Documented features of new Arria 10 variations:
    • User logic must configure external PLLs.
    • IP core includes reconfiguration controller.
    • IP core includes new Avalon-MM interface to program Arria 10 Native PHY IP core registers.
    • IP core does not support all of the hidden parameters.
    • IP core does not support temperature register and other registers related to unsupported parameters.
    • IP core provides a different process to enable the PRBS and CRC32 error injection testing features in Arria 10 variations.
  • Corrected recommended simulation value for Meta frame length in words parameter, from 64 (an unsupported value) to 128 (the minimum supported value).

November 2013

13.1 (2013.11.04)

  • Updated IP core generation instructions to indicate the MegaWizard Plug-In Manager no longer prompts the user to generate or not generate the example design. Instead, the example design is generated in all cases.
  • Provided additional information about TEMP_SENSE register.
  • Corrected typo in width of itx_hungry signal.
  • Modified introduction of resource utilization information to clarify that the numbers do not include the out-of-band flow control block.
  • Added OpenCore Plus feature support in Installation and Licensing section.

May 2013

13.0

Initial release.

Level Two Title