50G Interlaken MegaCore Function User Guide

ID 683217
Date 9/20/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.4. Files Generated for Intel® Arria® 10 Variations

The Quartus® Prime software generates multiple files during generation of your 50G Interlaken IP core Intel® Arria® 10 variation.

Figure 5. IP Core Generated Files

In the Quartus Prime software v15.1 release, generating a 50G Interlaken IP core that targets an Intel® Arria® 10 device does not generate a demonstration testbench. To generate the Verilog HDL testbench and example design files in this release, you must click the Generate Example Design button in the 50G Interlaken parameter editor. When you do so, you are prompted to specify the location of the Verilog HDL demonstration testbench and example design files.