50G Interlaken MegaCore Function User Guide

ID 683217
Date 9/20/2022

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3.2. Enable Native XCVR PHY ADME

The Enable Native XCVR PHY ADME parameter specifies whether your Arria 10 50G Interlaken IP core variation supports the ADME feature.

This parameter exposes debugging features of the Arria 10 Native PHY IP core that specifies the transceiver settings in the 50G Interlaken IP core. You can turn this parameter on to enable the following Arria 10 Native PHY IP core features:

  • Enable Altera Debug Master Endpoint (ADME)
  • Enable capability registers
  • Enable prbs soft accumulators
  • Enable odi acceleration logic

A checkmark in the check box to the left of the parameter turns this parameter on. When the parameter is turned on, the IP core include these transceiver reconfiguration capabilities. A check box with no checkmark indicates that the option is turned off, and the IP core does not support these features.

By default, the Enable native XCVR PHY ADME parameter is turned off.

This parameter is available only for 50G Interlaken IP core variations that target an Arria 10 device.