External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 11/03/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

11.5.9. Try Other Configurations

Designs are often quite large, using multiple blocks of IP in many different combinations. Determine whether any other configurations work correctly on the development platform.

The full project may have multiple external memory controllers in the same device, or may have configurations where only half the memory width or frequency is required. Find out what does and does not work to help the debugging of the issue.