External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 11/03/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.3. dramtiming0

address=20(32 bit)

Field Bit High Bit Low Description Access
cfg_tcl 6 0 Memory read latency. Read
Reserved 31 7 Reserved. Read