External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 11/03/2022

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Document Table of Contents Calibration Report Tab

The Calibration Report tab shows calibration status.

Choosing the Iteration to View

You may choose to view the Status, Delay Settings, or Margins reports for any of the most recent calibration iterations initiated through the toolkit. To select the iteration to view, select from the Iteration to Display dropdown menu.

ODT Settings in Effect

This report shows the ODT settings for the latest calibration.

Figure 179. ODT Settings

Calibration Status Report

The Calibration Status Report displays the calibration status and memory parity (ALERT_N) status. If a failure occurs, this report shows the first stage of calibration that failed, as well as the data groups that failed at this stage. Memory parity status observed during calibration is shown for DDR4 interfaces if ISSPs are enabled in the design. The calibration status report window contains a status indicator for memory parity and a button that allows you to reread memory parity status.

Calibration Delays and Margins Reports

These reports provide detailed information about the margins observed during calibration, and the settings applied on the calibration bus during calibration. To view the margins, click on the respective section for DQ, DQS, DM_DBI, Vref , or Address/Command.

Figure 180. DQ Margins
Figure 181. DQS Margins
Figure 182. DM_DBI Margins
Figure 183. Vref Settings
Figure 184. Address/Command Margins

These reports can also be viewed in a graphical format. Refer to Viewing Reports Graphically in the Eye Viewer.