External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 11/03/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.4.3.1. QDR-IV Single Device Memory Topology

This topic provides routing guidelines for a QDR-IV single-device memory topology.

The following figure illustrates the signal connection topology for a QDR-IV single-device memory configuration.

Figure 148. Signal Connections for QDR-IV Single Device Configuration
Table 148.  Specific Routing Guidelines for QDR-IV Single Device Memory Topology for Supported Signals in the Interface
Signal Group Segment Routing Layer Max Length (mil) Target Zse (ohm) Trace Width, W (mil) Trace Spacing, S1 (mil): Within Group Trace Spacing, S2 (mil): CMD/CTRL/CLK to DQ/DK/QK Trace Spacing, S3 (mil): Byte to Byte Trace Spacing, (mil), Within DIFF pair Trace Spacing, (mil), DK/QK pair to DQ Trace Spacing, (mil), CLK pair to CMD/CRTL/CKE
Segment Total MB
DQ, CMD, CTRL BO1 US 50 4000   4 5, 17 5, 17 17      
BO2 SL 1000   4 5, 17 5, 17 17      
M SL   45 4.5 8 (2H) 12 (3H) 12 (3H)      
BI US 150   4 8 (2H) 12 (3H) 12 (3H)      
DK/QK, CLK BO1 US 50 4000   4   5, 17   4 17 17
BO2 SL 1000   4   5, 17   4 17 17
M SL   45 4.5   12 (3H)   4 12 (3H) 12 (3H)
BI US 150   4   12 (3H)   4 12 (3H) 12 (3H)

For related information, refer to the figures in the Reference Stackup topic in this chapter.