Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide

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ID 683207
Date 7/27/2021
Public

5. Performing Intel® Stratix® 10 Boundary-Scan Testing

You can issue BYPASS, IDCODE, and SAMPLE JTAG instructions before, after, or during configuration without having to interrupt configuration.

To interrupt configuration in order to perform BST, you can either hold nCONFIG low or issue the following sequence via JTAG: an IR scan updating with 0x201 (COMMAND) followed by two 34 bit DR scans updating with 34’h3_0000_0000 then 35’h1_0000_0005. Once configuration is interrupted, you can issue other JTAG instructions to perform BST.

If you design a board for JTAG configuration using Intel® Stratix® 10 devices, consider the connections for the dedicated configuration pins.

Note: Dummy bits exist in the boundary-scan register during boundary-scan operations in Intel® Stratix® 10 devices. However, these dummy bits do not have any impact on the pins. The dummy bits appear on the TDO immediately before the corresponding boundary-scan register segment and have an unknown value X, which can be either a 0 or 1.

SoC Devices

For SoC device, you can only see the FPGA TAP controller in the JTAG chain upon device power up. The TAP controller for the HPS component only appears in the JTAG chain once the device is configured with a programming file/design containing the HPS component. You need to include the information about the HPS component when generating the test patterns for boundary-scan testing. You can download the boundary-scan description language (BSDL) file for the SoC device from the Intel® Stratix® 10 Device BSDL Files page.

1SG040 and 1SX040 Devices

For 1SG040 and 1SX040 devices, you must follow the guidelines to perform BST on I/O bank 3C to avoid broken chain in the device.

Table 6.  Boundary-Scan Cell Location and the Corresponding I/O PinsYou must set a constant value on the dedicated boundary-scan cell.
Boundary-Scan Cell Location in BSDL File Boundary-Scan Cell Value I/O Pins Location
469 1 U3, V3, U5, V4, W2, Y1, W3, W4
466 0
457 5

0 = output

1 = input

577 1 Y2, AA2, AB1, AB2, AC1, AD1, AF2, AG2
586 0
574 5

0 = output

1 = input

481 1 AE1, AE2, AD2, AD3, AF3, AF4, AG3, AH3
478 0
454 5

0 = output

1 = input

583 1 AG1, AH1, AJ1, AK1, AJ2, AJ3, AK2, AL2
589 0
580 5

0 = output

1 = input

475 1 AE4, AE5, Y4, AA4, AA3, AB3, AC3, AD4
472 0
463 5

0 = output

1 = input

451 1 AM1, AM2, Y5, AA5, AC4, AB5, AC5, AB6
460 0
448 5

0 = output

1 = input

5 Set this boundary-scan cell to '0' to perform drive-out test on the listed I/O pins. Set to ‘1’ to perform capture test on the listed I/O pins.

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