Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide

Download PDF
ID 683207
Date 7/27/2021
Public

Visible to Intel only — GUID: sss1438252032470

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Overview 2. Intel® Stratix® 10 JTAG BST Architecture 3. Intel® Stratix® 10 BST Operation Control 4. Intel® Stratix® 10 I/O Voltage for JTAG Operation 5. Performing Intel® Stratix® 10 Boundary-Scan Testing 6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry 7. Intel® Stratix® 10 IEEE Std. 1149.1 BST Guidelines 8. Document Revision History for the Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide
2. Intel® Stratix® 10 JTAG BST Architecture x
2.1. JTAG Circuitry Functional Model 2.2. JTAG Pins 2.3. IEEE Std. 1149.1 Boundary-Scan Register 2.4. IEEE Std. 1149.6 Boundary-Scan Register
2.3. IEEE Std. 1149.1 Boundary-Scan Register x
2.3.1. Boundary-Scan Cells of Intel® Stratix® 10 Device I/O Pin
2.4. IEEE Std. 1149.6 Boundary-Scan Register x
2.4.1. IEEE Std. 1149.6 BST Circuitry for Intel® Stratix® 10 E-Tile Transceiver 2.4.2. IEEE Std. 1149.6 BST Circuitry for Intel® Stratix® 10 P-Tile Transceiver
3. Intel® Stratix® 10 BST Operation Control x
3.1. Device ID 3.2. Supported JTAG Instructions 3.3. JTAG Secure Mode
6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry x
6.1. Enabling BST Circuitry 6.2. Disabling BST Circuitry
1. Intel® Stratix® 10 Overview
2. Intel® Stratix® 10 JTAG BST Architecture
3. Intel® Stratix® 10 BST Operation Control
4. Intel® Stratix® 10 I/O Voltage for JTAG Operation
5. Performing Intel® Stratix® 10 Boundary-Scan Testing
6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry
7. Intel® Stratix® 10 IEEE Std. 1149.1 BST Guidelines
8. Document Revision History for the Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide

4. Intel® Stratix® 10 I/O Voltage for JTAG Operation

The Intel® Stratix® 10 device operating in IEEE Std. 1149.1 and IEEE Std. 1149.6 modes uses four required JTAG pins—TDI, TDO, TMS, and TCK.

The TCK pin has an internal weak pull-down resistor, while the TDI and TMS pins have internal weak pull-up resistors. The VCCIO_SDM supply powers the TDI, TDO, TMS, and TCK pins.

The JTAG pins support 1.8 V TTL/CMOS I/O standard.

Note: For any voltages higher than 1.8 V, you have to use level shifter. The output voltage of the level shifter for the JTAG pins must be the same as set for the VCCIO_SDM supply.
Table 5.  TDO Output Buffer
TDO Output Buffer Condition Voltage (V)
VCCIO_SDM 1.8
Level Two Title