Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide

Download
ID 683207
Date 7/27/2021
Public

4. Intel® Stratix® 10 I/O Voltage for JTAG Operation

The Intel® Stratix® 10 device operating in IEEE Std. 1149.1 and IEEE Std. 1149.6 modes uses four required JTAG pins—TDI, TDO, TMS, and TCK.

The TCK pin has an internal weak pull-down resistor, while the TDI and TMS pins have internal weak pull-up resistors. The VCCIO_SDM supply powers the TDI, TDO, TMS, and TCK pins.

The JTAG pins support 1.8 V TTL/CMOS I/O standard.

Note: For any voltages higher than 1.8 V, you have to use level shifter. The output voltage of the level shifter for the JTAG pins must be the same as set for the VCCIO_SDM supply.
Table 5.  TDO Output Buffer
TDO Output Buffer Condition Voltage (V)
VCCIO_SDM 1.8

Did you find the information on this page useful?

Characters remaining:

Feedback Message