Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide
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Visible to Intel only — GUID: sss1438252032470
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4. Intel® Stratix® 10 I/O Voltage for JTAG Operation
The Intel® Stratix® 10 device operating in IEEE Std. 1149.1 and IEEE Std. 1149.6 modes uses four required JTAG pins—TDI, TDO, TMS, and TCK.
The TCK pin has an internal weak pull-down resistor, while the TDI and TMS pins have internal weak pull-up resistors. The VCCIO_SDM supply powers the TDI, TDO, TMS, and TCK pins.
The JTAG pins support 1.8 V TTL/CMOS I/O standard.
TDO Output Buffer Condition | Voltage (V) |
---|---|
VCCIO_SDM | 1.8 |