Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide

Download
ID 683207
Date 7/27/2021
Public

6.2. Disabling BST Circuitry

To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.

Table 7.  Pin Connections to Permanently Disable the IEEE Std. 1149.1 Circuitry for Intel® Stratix® 10 Devices
JTAG Pins6 Connection for Disabling
TMS VCCIO_SDM
TCK GND
TDI VCCIO_SDM
TDO Leave open
6 The JTAG pins are dedicated. Software option is not available to disable JTAG in Intel® Stratix® 10 devices.

Did you find the information on this page useful?

Characters remaining:

Feedback Message