Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide

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ID 683207
Date 7/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Overview 2. Intel® Stratix® 10 JTAG BST Architecture 3. Intel® Stratix® 10 BST Operation Control 4. Intel® Stratix® 10 I/O Voltage for JTAG Operation 5. Performing Intel® Stratix® 10 Boundary-Scan Testing 6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry 7. Intel® Stratix® 10 IEEE Std. 1149.1 BST Guidelines 8. Document Revision History for the Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide
2. Intel® Stratix® 10 JTAG BST Architecture x
2.1. JTAG Circuitry Functional Model 2.2. JTAG Pins 2.3. IEEE Std. 1149.1 Boundary-Scan Register 2.4. IEEE Std. 1149.6 Boundary-Scan Register
2.3. IEEE Std. 1149.1 Boundary-Scan Register x
2.3.1. Boundary-Scan Cells of Intel® Stratix® 10 Device I/O Pin
2.4. IEEE Std. 1149.6 Boundary-Scan Register x
2.4.1. IEEE Std. 1149.6 BST Circuitry for Intel® Stratix® 10 E-Tile Transceiver 2.4.2. IEEE Std. 1149.6 BST Circuitry for Intel® Stratix® 10 P-Tile Transceiver
3. Intel® Stratix® 10 BST Operation Control x
3.1. Device ID 3.2. Supported JTAG Instructions 3.3. JTAG Secure Mode
6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry x
6.1. Enabling BST Circuitry 6.2. Disabling BST Circuitry
1. Intel® Stratix® 10 Overview
2. Intel® Stratix® 10 JTAG BST Architecture
3. Intel® Stratix® 10 BST Operation Control
4. Intel® Stratix® 10 I/O Voltage for JTAG Operation
5. Performing Intel® Stratix® 10 Boundary-Scan Testing
6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry
7. Intel® Stratix® 10 IEEE Std. 1149.1 BST Guidelines
8. Document Revision History for the Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide
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3.2. Supported JTAG Instructions

Table 4.  JTAG Instructions Supported by Intel® Stratix® 10 Devices
CAUTION:
Never invoke instruction codes other than the supported JTAG instructions in the following table. Invoking unsupported instruction can damage and render the device unusable.
JTAG Instruction Instruction Code Description
MISCCTRL 00 0001 0011
  • Required instruction to enable the boundary-scan circuitry for JTAG BST.
  • Set the LSB of the 8-bit data register to '1' and the remaining bits to '0' to enable the boundary-scan circuitry.
SAMPLE 4/PRELOAD 00 0000 0101
  • Allows you to capture and examine a snapshot of signals at the device pins during normal device operation and permits an initial data pattern to be an output at the device pins.
  • Use this instruction to preload the test pattern into the update registers before loading the EXTEST instruction.
EXTEST 00 0000 1111
  • Board-level interconnects by forcing a test pattern at the output pins, and capturing the test results at the input pins. Forcing known logic high and low levels on output pins allows you to detect opens and shorts at the pins of any device in the scan chain.
  • The high-impedance state of EXTEST is overridden by bus hold and weak pull-up resistor features.
BYPASS 11 1111 1111
  • Places the 1-bit bypass register between the TDI and TDO pins. During normal device operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices.
  • You will get a '0' reading in the bypass register out.
USERCODE 00 0000 0111
  • Selects the 32-bit USERCODE register and places it between the TDI and TDO pins to allow serial shifting of USERCODE out of TDO.
  • The 32-bit USERCODE is a programmable user-defined pattern.
IDCODE 00 0000 0110
  • Identifies the devices in a JTAG chain. When the IDCODE register is selected by the IR then in the CAPTURE_DR state, the IDCODE instruction places the 32-bit Device ID register between the TDI and TDO pins to allow serial shifting of Device ID out of TDO.
  • Selects the Device ID register and places it between the TDI and TDO pins to allow serial shifting of Device ID register out of TDO.
  • IDCODE instruction is the default instruction in the Test-Logic-Reset state.
HIGHZ 00 0000 1011
  • Sets all user I/O pins to an inactive drive state.
  • Places the 1-bit bypass register between the TDI and TDO pins.
  • The programmable weak pull-up resistor or the bus hold feature overrides the HIGHZ value at the pin.
CLAMP 00 0000 1010
  • Places the 1-bit bypass register between the TDI and TDO pins.
  • The programmable weak pull-up resistor or the bus hold feature overrides the CLAMP value at the pin. The CLAMP value is the value stored in the update register of the boundary-scan cell (BSC).
EXTEST_PULSE 00 1000 1111 Enables board-level connectivity checking between the transmitters and receivers that are AC coupled by generating three output transitions:
  • Driver drives data on the falling edge of TCK in the UPDATE_IR/DR state.
  • Driver drives inverted data on the falling edge of TCK after entering the RUN_TEST/IDLE state.
  • Driver drives data on the falling edge of TCK after leaving the RUN_TEST/IDLE state.
EXTEST_TRAIN 00 0100 1111 Behaves the same as the EXTEST_PULSE instruction except that the output continues to toggle on the TCK falling edge provided that the TAP controller is in the RUN_TEST/IDLE state.
Related Information
4 SAMPLE instruction is not supported for high-speed serial interface (HSSI) pins.
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