Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide

ID 683207
Date 7/27/2021

2.1. JTAG Circuitry Functional Model

The JTAG BST circuitry requires the following registers:

  • Instruction register—determines which action to perform and which data register to access.
  • Bypass register (1-bit long data register)—provides a minimum-length serial path between the TDI and TDO pins.
  • Boundary-scan register—shift register composed of all the BSCs of the device.
Figure 1. JTAG Circuitry Functional Model
  • Test access port (TAP) controller—controls the JTAG BST.
  • TMS and TCK pins—operate the TAP controller.
  • TDI and TDO pins—provide the serial path for the data and instruction registers.
Note: TRST pin is not available in Intel® Stratix® 10 devices.

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