Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide

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ID 683207
Date 7/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Overview 2. Intel® Stratix® 10 JTAG BST Architecture 3. Intel® Stratix® 10 BST Operation Control 4. Intel® Stratix® 10 I/O Voltage for JTAG Operation 5. Performing Intel® Stratix® 10 Boundary-Scan Testing 6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry 7. Intel® Stratix® 10 IEEE Std. 1149.1 BST Guidelines 8. Document Revision History for the Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide
2. Intel® Stratix® 10 JTAG BST Architecture x
2.1. JTAG Circuitry Functional Model 2.2. JTAG Pins 2.3. IEEE Std. 1149.1 Boundary-Scan Register 2.4. IEEE Std. 1149.6 Boundary-Scan Register
2.3. IEEE Std. 1149.1 Boundary-Scan Register x
2.3.1. Boundary-Scan Cells of Intel® Stratix® 10 Device I/O Pin
2.4. IEEE Std. 1149.6 Boundary-Scan Register x
2.4.1. IEEE Std. 1149.6 BST Circuitry for Intel® Stratix® 10 E-Tile Transceiver 2.4.2. IEEE Std. 1149.6 BST Circuitry for Intel® Stratix® 10 P-Tile Transceiver
3. Intel® Stratix® 10 BST Operation Control x
3.1. Device ID 3.2. Supported JTAG Instructions 3.3. JTAG Secure Mode
6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry x
6.1. Enabling BST Circuitry 6.2. Disabling BST Circuitry
1. Intel® Stratix® 10 Overview
2. Intel® Stratix® 10 JTAG BST Architecture
3. Intel® Stratix® 10 BST Operation Control
4. Intel® Stratix® 10 I/O Voltage for JTAG Operation
5. Performing Intel® Stratix® 10 Boundary-Scan Testing
6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry
7. Intel® Stratix® 10 IEEE Std. 1149.1 BST Guidelines
8. Document Revision History for the Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide

2.4. IEEE Std. 1149.6 Boundary-Scan Register

The BSCs for HSSI transmitters ( GXB_TX[p,n] ) and receivers/input clock buffers (GXB_RX[p,n]) /(REFCLK[p,n]) in Intel® Stratix® 10 devices are different from the BSCs for the I/O pins.

Note: You have to use the EXTEST_PULSE JTAG instruction for AC-coupling on HSSI transceiver. Do not use the EXTEST JTAG instruction for AC-coupling on HSSI transceiver. You can perform AC JTAG on the Intel® Stratix® 10 device before, after, and during configuration.
Figure 4. HSSI Transmitter BSC for Intel® Stratix® 10 Devices


Figure 5. HSSI Receiver/Input Clock Buffer for Intel® Stratix® 10 Devices


Figure 6. UIB and eSRAM BSC for Intel® Stratix® 10 DevicesThe differential reference clock input pins for UIB and eSRAM are sharing the BSC per pair as shown in this figure. The capture value (DATAIN) would be invalid if one or both differential inputs are abnormal.
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