Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 6/22/2022
Public
Document Table of Contents

2.4.1.2. Clock Enable in Memory Blocks

In memory blocks, power consumption is tied to the clock rate, and is insensitive to the toggle rate on the data and address lines. Memory consumes approximately 20% of the core dynamic power in typical designs.

When a memory block is clocked, a sequence of timed events occur within the block to execute a read or write. The circuitry that the clock controls consumes the same amount of power, independent of changes in address or data from one cycle to the next. Thus, the toggle rate of input data and the address bus have no impact on memory power consumption.

The key to reducing memory power consumption is to reduce the number of memory clocking events. You can achieve this reduction through network-wide clock gating, or on a per-memory basis through use of the clock enable signals on the memory ports.

Figure 23. Memory Clock Enable SignalLogical view of the internal clock of the memory block. Use the appropriate enable signals on the memory to make use of the clock enable signal instead of gating the clock.

The clock enable signal enables the memory only when necessary, and shuts down for the rest of the time, reducing the overall memory power consumption. You include these enable signals when generating the memory block function.

Figure 24. Clock Enable in RAM 2-Port

The Intel® Quartus® Prime software automatically chooses the best design memory configuration for optimal power. However, you can set the MAXIMUM_DEPTH parameter for memory modules during the IP core instantiation.

Figure 25. RAM 2-Port Maximum Depth

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