Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

ID 683240
Date 9/17/2021
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3.7. Clocking Modes and Clock Enable

The embedded memory block supports various types of clocking modes depending on the memory mode you select.
Table 7.  Clocking Modes
Clocking Modes Description
Single Clock Mode In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory block.
Read/Write Clock Mode In the read/write clock mode:
  • A read clock controls the data-output, read-address, and read-enable registers.
  • A write clock controls the data-input, write-address, write-enable, and byte enable registers.
Input/Output Clock Mode In input/output clock mode:
  • An input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables.
  • An output clock controls the data output registers.
Independent Clock Mode In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side.
Note: You can create independent clock enable for different input and output registers to control the shut down of a particular register for power saving purposes. From the parameter editor, click More Options (beside the clock enable option) to set the available independent clock enable that you prefer.
Table 8.  Clocking ModesThis table lists the embedded memory clocking modes.
Clocking Modes Single-port RAM Simple Dual-port RAM True Dual-port RAM Single-port ROM Dual-port ROM
Single clock Supported Supported Supported Supported Supported
Read/Write Supported
Input/Output Supported Supported Supported Supported Supported
Independent Supported Supported
Note: Asynchronous clock mode is only supported in MAX series of devices, and not supported in Stratix and newer devices. However, newer devices support asynchronous read memory for simple dual-port RAM mode if you choose MLAB memory block with unregistered rdaddress port.
Note: The clock enable signals are not supported for write address, byte enable, and data input registers on Arria V, Cyclone V, and Stratix V MLAB blocks.