Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

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ID 683240
Date 9/17/2021
Public
Document Table of Contents
Document Table of Contents x
1. About Embedded Memory IP Cores 2. Embedded Memory IP Cores Getting Started 3. Functional Description 4. Embedded Memory Design Consideration 5. Parameters and Signals 6. Design Example 7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
1. About Embedded Memory IP Cores x
1.1. Features
2. Embedded Memory IP Cores Getting Started x
2.1. Changing Parameter Settings Manually 2.2. RAM and ROM Parameter Settings
3. Functional Description x
3.1. Memory Block Types 3.2. Write and Read Operations Triggering 3.3. Port Width Configurations 3.4. Mixed-width Port Configuration 3.5. Mixed-width Ratio Configuration 3.6. Maximum Block Depth Configuration 3.7. Clocking Modes and Clock Enable 3.8. Memory Blocks Address Clock Enable Support 3.9. Byte Enable 3.10. Asynchronous Clear 3.11. Read Enable 3.12. Read-During-Write 3.13. Power-Up Conditions and Memory Initialization 3.14. Error Correction Code 3.15. Freeze Logic
3.12. Read-During-Write x
3.12.1. Selecting RDW Output Choices for Various Memory Blocks
4. Embedded Memory Design Consideration x
4.1. Avoid Providing Non-Deterministic Input
5. Parameters and Signals x
5.1. RAM: 1-Port IP Core Parameters 5.2. RAM: 2-Port IP Core Parameters 5.3. ROM: 1-PORT IP Core Parameters 5.4. ROM: 2-PORT IP Core Parameters 5.5. Signals
6. Design Example x
6.1. External ECC Implementation with True-Dual-Port RAM
6.1. External ECC Implementation with True-Dual-Port RAM x
6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core 6.1.2. Simulating the Design
6.1.2. Simulating the Design x
6.1.2.1. Simulation Results
1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

5.5. Signals

Table 20.  Interface Signals of the Embedded Memory IP Cores
Signal Type Required Description
data_a Input Optional Data input to port A of the memory.

The data_a port is required if you set the operation_mode parameter to any of the following values:

  • SINGLE_PORT
  • DUAL_PORT
  • BIDIR_DUAL_PORT
address_a Input Yes Address input to port A of the memory.

The address_a signal is required for all operation modes.

wren_a Input Optional Write enable input for address_a port.

The wren_a signal is required if you set the operation_mode to any of the following values:

  • SINGLE_PORT
  • DUAL_PORT
  • BIDIR_DUAL_PORT
rden_a Input Optional Read enable input for address_a port. The rden_a signal is supported depending on your selected memory mode and memory block.
byteena_a Input Optional Byte enable input to mask the data_a port so that only specific bytes, nibbles, or bits of the data are written.

The byteena_a port is not supported in the following conditions:

  • If implement_in_les parameter is set to ON
  • If operation_mode parameter is set to ROM
addressstall_a Input Optional Address clock enable input to hold the previous address of address_a port for as long as the addressstall_a port is high.
q_a Output Yes Data output from port A of the memory.

The q_a port is required if the operation_mode parameter is set to any of the following values:

  • SINGLE_PORT
  • BIDIR_DUAL_PORT
  • ROM
The width of q_a port must be equal to the width of data_a port.
data_b Input Optional Data input to port B of the memory.

The data_b port is required if the operation_mode parameter is set to BIDIR_DUAL_PORT.

address_b Input Optional Address input to port B of the memory.

The address_b port is required if the operation_mode parameter is set to the following values:

  • DUAL_PORT
  • BIDIR_DUAL_PORT
wren_b Input Yes Write enable input for address_b port.

The wren_b port is required if operation_mode is set to BIDIR_DUAL_PORT.

rden_b Input Optional Read enable input for address_b port. The rden_b port is supported depending on your selected memory mode and memory block
byteena_b Input Optional Byte enable input to mask the data_b port so that only specific bytes, nibbles, or bits of the data are written.

The byteena_b port is not supported in the following conditions:

  • If implement_in_les parameter is set to ON
  • If operation_mode parameter is set to SINGLE_PORT, DUAL_PORT, or ROM
addressstall_b Input Optional Address clock enable input to hold the previous address of address_b port for as long as the addressstall_b port is high.
q_b Output Yes Data output from port B of the memory. The q_b port is required if the operation_mode is set to the following values:
  • DUAL_PORT
  • BIDIR_DUAL_PORT

The width of q_b port must be equal to the width of data_b port.

clock0 Input Yes The following describes which of your memory clock must be connected to the clock0 port, and port synchronization in different clocking modes:
  • Single clock: Connect your single source clock to clock0 port. All registered ports are synchronized by the same source clock.
  • Read/Write: Connect your write clock to clock0 port. All registered ports related to write operation, such as data_a port, address_a port, wren_a port, and byteena_a port are synchronized by the write clock.
  • Input Output: Connect your input clock to clock0 port. All registered input ports are synchronized by the input clock.
  • Independent clock: Connect your port A clock to clock0 port. All registered input and output ports of port A are synchronized by the port A clock.
clock1 Input Optional The following describes which of your memory clock must be connected to the clock1 port, and port synchronization in different clocking modes:
  • Single clock: Not applicable. All registered ports are synchronized by clock0 port.
  • Read/Write: Connect your read clock to clock1 port. All registered ports related to read operation, such as address_b port, rden_b port, and q_b port are synchronized by the read clock.
  • Input Output: Connect your output clock to clock1 port. All the registered output ports are synchronized by the output clock.
  • Independent clock: Connect your port B clock to clock1 port. All registered input and output ports of port B are synchronized by the port B clock.
clocken0 Input Optional Clock enable input for clock0 port.
clocken1 Input Optional Clock enable input for clock1 port.
clocken2 Input Optional Clock enable input for clock0 port.
clocken3 Input Optional Clock enable input for clock1 port.
aclr0

aclr1

Input Optional Asynchronously clear the registered input and output ports. The aclr0 port affects the registered ports that are clocked by clock0 clock, while the aclr1 port affects the registered ports that are clocked by clock1 clock.

The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as outdata_aclr_a,address_aclr_a, and so on.

eccstatus Output Optional A 3-bit wide error correction status port. Indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit occurs.

In Stratix V devices, the M20K ECC status is communicated with two-bit wide error correction status port. The M20K ECC detects and fixes a single bit error event or a double adjacent error event, or detects three adjacent errors without fixing the errors.

The eccstatus port is supported if all the following conditions are met:

  • operation_mode parameter is set to DUAL_PORT
  • ram_block_type parameter is set to M144K or M20K
  • width_a and width_b parameter have the same value
  • Byte enable is not used
data Input Yes Data input to the memory. The data port is required and the width must be equal to the width of the q port.
wraddress Input Yes Write address input to the memory. The wraddress port is required and must be equal to the width of the raddress port.
wren Input Yes Write enable input for wraddress port. The wren port is required.
rdaddress Input Yes Read address input to the memory. The rdaddress port is required and must be equal to the width of wraddress port.
rden Input Optional Read enable input for rdaddress port. The rden port is supported when the use_eab parameter is set to OFF. The rden port is not supported when the ram_block_type parameter is set to MLAB. Instantiate the ALTSYNCRAM IP core if you want to use read enable feature with other memory blocks.
byteena Input Optional Byte enable input to mask the data port so that only specific bytes, nibbles, or bits of data are written. The byteena port is not supported when use_eab parameter is set to OFF. It is supported in Arria II GX and newer devices with the ram_block_type parameter set to MLAB.
wraddressstall Input Optional Write address clock enable input to hold the previous write address of wraddress port for as long as the wraddressstall port is high.
rdaddressstall Input Optional Read address clock enable input to hold the previous read address of rdaddress port for as long as the wraddressstall port is high. The rdaddressstall port is only supported in newer devices except when the rdaddress_reg parameter is set to UNREGISTERED.
q Output Yes Data output from the memory. The q port is required, and must be equal to the width data port.
inclock Input Yes The following describes which of your memory clock must be connected to the inclock port, and port synchronization in different clocking modes:
  • Single clock: Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock.
  • Read/Write: Connect your write clock to inclock port. All registered ports related to write operation, such as data port, wraddress port, wren port, and byteena port are synchronized by the write clock.
  • Input/Output: Connect your input clock to inclock port. All registered input ports are synchronized by the input clock.
outclock Input Yes The following describes which of your memory clock must be connected to the outclock port, and port synchronization in different clocking modes:
  • Single clock: Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock.
  • Read/Write: Connect your read clock to outclock port. All registered ports related to read operation, such as rdaddress port, rdren port, and q port are synchronized by the read clock.
  • Input/Output: Connect your output clock to outclock port. The registered q port is synchronized by the output clock.
inclocken Input Optional Clock enable input for inclock port.
outclocken Input Optional Clock enable input for outclock port.
aclr Input Optional Asynchronously clear the registered input and output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as indata_aclr, wraddress_aclr, and so on.
Note: When running the embedded memory simulation model, you must ensure that you do not provide “X” or dont_care as inputs to the simulation model. Providing “X” or don’t_care may result in unexpected behavior in simulation.
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