Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

ID 683240
Date 9/17/2021
Public
Document Table of Contents
Give Feedback

3.8. Memory Blocks Address Clock Enable Support

The embedded memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signal is low (disabled).

Figure 3. Address Clock EnableThis figure shows an address clock enable block diagram. The address clock enable is referred to by the port name addressstall.


Figure 4. Address Clock Enable During Read Cycle WaveformThis figure shows the address clock enable waveform during the read cycle.


Figure 5. Address Clock Enable During the Write Cycle WaveformThis figure shows the address clock enable waveform during the write cycle.