Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

ID 683240
Date 9/17/2021
Public
Document Table of Contents
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3.15. Freeze Logic

The freeze logic feature specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region.
This feature is applicable only to the RAM modes:
  • Single-port RAM
  • Dual-port RAM

You have the option to turn on Implement clock-enable circuitry for use in a partial reconfiguration to enable the freeze logic feature in the parameter editors of the RAM/ROM IP cores.