Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

ID 683240
Date 9/17/2021
Public
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6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core

To generate the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP core, follow these steps:

  1. Open the Internal_Memory_DesignExample.zip file and extract true_dp.qar.
  2. In the Intel® Quartus® Prime software, open the true_dp.qar file and restore the archive file into your working directory.
  3. In the IP Catalog (Tools > IP Catalog), locate and double-click the ALTECC IP core. The parameter editor appears.
  4. Specify the following parameters:
    Table 21.  Configuration Settings for ALTECC_ENCODER
    Option Value
    How do you want to configure this module? Configure this module as an ECC encoder
    How wide should the data be? 8 bits
    Do you want to pipeline the functions? Yes, I want an output latency of 1 clock cycle
    Create an 'aclr' asynchronous clear port Not selected
    Create a 'clocken' clock enable clock Not selected
  5. Click Finish. The ecc_encoder.v module is built.
  6. In the IP Catalog double-click the ALTECC IP core. The parameter editor appears.
  7. Specify the following parameters:
    Table 22.  Configuration Settings for ALTECC_DECODER
    Option Value
    How do you want to configure this module? Configure this module as an ECC decoder
    How wide should the data be? 13 bits
    Do you want to pipeline the functions? Yes, I want an output latency of 1 clock cycle
    Create an 'aclr' asynchronous clear port Not selected
    Create a 'clocken' clock enable clock Not selected
  8. Click Finish. The ecc_decoder.v module is built.
  9. In the IP Catalog double-click the ALTECC IP core. The parameter editor appears.
  10. Specify the following parameters:
    Table 23.  Configuration Settings for RAM: 2-Port IP Core
    Option Value
    Which type of output file do you want to create? Verilog HDL
    What name do you want for the output file? true_dp_ram
    Return to this page for another create operation Turned off
    Currently selected device family: Stratix IV
    How will you be using the dual port ram? With two read/write ports
    How do you want to specify the memory size? As a number of words
    How many 8-bit words of memory? 16
    Use different data widths on different ports Not selected
    How wide should the 'q_a' output bus be? 13
    What should the memory block type be? M9K
    Set the maximum block depth to Auto
    Which clocking method do you want to use? Single clock
    Create 'rden_a' and 'rden_b' read enable signals Not selected
    Byte Enable Ports Not selected
    Which ports should be registered? All write input ports and read output ports
    Create one clock enable signal for each signal Not selected
    Create an 'aclr' asynchronous clear for the registered ports Not selected
    Mixed Port Read-During-Write for Single Input Clock RAM Old memory contents appear
    Port A Read-During-Write Option New Data
    Port B Read-During-Write Option Old Data
    Do you want to specify the initial content of the memory? Not selected
    Generate netlist Turned off
    Variation file (.vhd) Turned on
    AHDL Include file (.inc) Turned off
    VHDL component declaration file (.cmp) Turned on
    Intel® Quartus® Prime symbol file (.bsf) Turned off
    Instantiation template file(.vhd) Turned off
  11. Click Finish. The true_dp_ram.v module is built.
The top_dpram.v is a design variation file that contains the top level file that instantiates two encoders, a true dual-port RAM, and two decoders. To simulate the design, a testbench, true_dp_ram.vt, is created for you to run in the ModelSim* - Intel® FPGA Edition software.