Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

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ID 683240
Date 9/17/2021
Public
Document Table of Contents
Document Table of Contents x
1. About Embedded Memory IP Cores 2. Embedded Memory IP Cores Getting Started 3. Functional Description 4. Embedded Memory Design Consideration 5. Parameters and Signals 6. Design Example 7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
1. About Embedded Memory IP Cores x
1.1. Features
2. Embedded Memory IP Cores Getting Started x
2.1. Changing Parameter Settings Manually 2.2. RAM and ROM Parameter Settings
3. Functional Description x
3.1. Memory Block Types 3.2. Write and Read Operations Triggering 3.3. Port Width Configurations 3.4. Mixed-width Port Configuration 3.5. Mixed-width Ratio Configuration 3.6. Maximum Block Depth Configuration 3.7. Clocking Modes and Clock Enable 3.8. Memory Blocks Address Clock Enable Support 3.9. Byte Enable 3.10. Asynchronous Clear 3.11. Read Enable 3.12. Read-During-Write 3.13. Power-Up Conditions and Memory Initialization 3.14. Error Correction Code 3.15. Freeze Logic
3.12. Read-During-Write x
3.12.1. Selecting RDW Output Choices for Various Memory Blocks
4. Embedded Memory Design Consideration x
4.1. Avoid Providing Non-Deterministic Input
5. Parameters and Signals x
5.1. RAM: 1-Port IP Core Parameters 5.2. RAM: 2-Port IP Core Parameters 5.3. ROM: 1-PORT IP Core Parameters 5.4. ROM: 2-PORT IP Core Parameters 5.5. Signals
6. Design Example x
6.1. External ECC Implementation with True-Dual-Port RAM
6.1. External ECC Implementation with True-Dual-Port RAM x
6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core 6.1.2. Simulating the Design
6.1.2. Simulating the Design x
6.1.2.1. Simulation Results
1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.09.17 17.0
  • Updated the descriptions for Read/Write Clock Mode and Input/Output Clock Mode in Table: Clocking Modes.
  • Updated the description for Dual clock: use separate ‘input’ and ‘output’ clocks in Tables: RAM: 1-Port Parameter Settings and RAM: 2-Port Parameter Settings.
2020.03.11 17.0
  • Updated the Design Example topic.
  • Restructured the document.
2019.10.22 17.0
  • Added new Topic—Avoid Providing Non-Deterministic Input.
  • Added a note to the RAM and ROM Interface Signals topic.
Date Version Changes
November 2017 2017.11.06
  • Updated the Changing Parameter Settings Manually topic.
  • Updated the Freeze Logic topic.
  • Updated "ROM: 2-PORT IP Core Parameters" table: Removed MLAB reference in legal values for memory block type.
  • Updated for latest branding standards.
  • Made editorial updates throughout the document.
May 2017 2017.05.08
  • Rebranded to Intel.
  • Updated to Embedded Memory IP Cores Getting Started topic with links to Introduction to IP core.
  • Updated the Features topic to include freeze logic feature support for RAM modes.
  • Updated the Write Operation description for MLAB blocks in the Write and Read Operations Triggering for Embedded Memory Blocks table.
  • Added Mixed-width Ratio Configuration topic.
  • Added Freeze Logic topic.
  • Added the Implement clock-enable circuitry for use in a partial reconfiguration region option for the RAM: 1-PORT and RAM: 2-PORT IP cores.
  • Added support for Cyclone 10 LP and GX device families.
  • Updated the legal value for operation_mode from TRUE_DUAL_PORT to BIDIR_DUAL_PORT in the Parameters for altera_syncram table.
  • Updated the Interface Signals of the Embedded Memory IP Cores table.
  • Updated the Configuration Settings for RAM: 2-Port IP Core table in the Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core topic.
  • Updated note in the Clocking Modes and Clock Enable topic to remove Stratix III.
  • Updated Quartus II to Intel® Quartus® Prime.
  • Minor typographical corrections.
May 2016 2016.05.02
  • Updated the About Embedded Memory IP Cores topics.
  • Added a new topic: Changing Parameter Settings Manually.
  • Updated the Memory Block Types topic to add the memory types for Arria 10 and MAX 10.
  • Updated the Error Correction Code topic.
December 2014 2014.12.17
  • Specified that to enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT IP cores.
  • Updated document template.
2014.06.30 5.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
  • Removed all references to obsolete SOPC Builder tool.
May 2014 4.4 Editorial fix to Table 4–1 on page 4–5.
November 2013 4.3 Updated Table 3–8 on page 3–18 to update M20K block information.
May 2013 4.2 Updated Table 3–4 on page 3–11 to fix a typographical error.
November 2012 4.1
  • Added a note to the “Asynchronous Clear” on page 3–15 to state that internal contents cannot be cleared with the asynchronous clear signal.
  • Updated note in “Clocking Modes and Clock Enable” on page 3–11 to include Stratix V devices.
  • Added a note to the “Asynchronous Clear” on page 3–15 to clarify that clear deassertion on output latch is dependent on output clock.
January 2012 4.0 Added a note to “Power-Up Conditions and Memory Initialization” section.
November 2011 3.0
  • Updated the RAM2:Port parameter settings.
  • Updated the Read-During-Write section. Added M10K memory block information.
  • Added support information for Arria V and Cyclone V.
March 2011 2.0 Added new features for M20K memory block.
November 2009 1.0 Initial release
Level Two Title