Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
ID
683240
Date
9/17/2021
Public
1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
3.1. Memory Block Types
3.2. Write and Read Operations Triggering
3.3. Port Width Configurations
3.4. Mixed-width Port Configuration
3.5. Mixed-width Ratio Configuration
3.6. Maximum Block Depth Configuration
3.7. Clocking Modes and Clock Enable
3.8. Memory Blocks Address Clock Enable Support
3.9. Byte Enable
3.10. Asynchronous Clear
3.11. Read Enable
3.12. Read-During-Write
3.13. Power-Up Conditions and Memory Initialization
3.14. Error Correction Code
3.15. Freeze Logic
2.1. Changing Parameter Settings Manually
When the IP has been generated using the IP Parameter Editor, you can use this flow to change of the parameter settings within the specified memory mode. However, to change the memory mode, use the IP Parameter Editor to configure and regenerate the IP.
Follow these steps to change the parameter settings manually:
- Locate the Verilog design file: <project directory>/<project name_software version>/synth/<projectName_coreName_QuartusVersion_random>.v.
- Change the parameter settings in the design file. Ensure that you use only legal parameter values as specified in Parameters and Signals topic. Failing to do so results in compilation errors.
- Compile the design using the Intel® Quartus® Prime software.
For example, the following codes enable the ECC feature and specify the initialization file.
altera_syncram_component.enable_ecc = "TRUE", altera_syncram_component.ecc_pipeline_stage_enabled = "FALSE", altera_syncram_component.init_file = "mif1.mif",
To disable the ECC feature and specify a different .mif file, make the following changes.
altera_syncram_component.enable_ecc = "FALSE", altera_syncram_component.ecc_pipeline_stage_enabled = "FALSE", altera_syncram_component.init_file = "mif2.mif",
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