Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
                    
                        ID
                        683240
                    
                
                
                    Date
                    9/17/2021
                
                
                    Public
                
            
                
                    
                        1. About Embedded Memory IP Cores
                    
                    
                
                    
                        2. Embedded Memory IP Cores Getting Started
                    
                    
                
                    
                        3. Functional Description
                    
                    
                
                    
                        4. Embedded Memory Design Consideration
                    
                    
                
                    
                        5. Parameters and Signals
                    
                    
                
                    
                        6. Design Example
                    
                    
                
                    
                    
                        7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
                    
                
            
        
                        
                        
                            
                            
                                3.1. Memory Block Types
                            
                        
                            
                            
                                3.2. Write and Read Operations Triggering
                            
                        
                            
                            
                                3.3. Port Width Configurations
                            
                        
                            
                            
                                3.4. Mixed-width Port Configuration
                            
                        
                            
                            
                                3.5. Mixed-width Ratio Configuration
                            
                        
                            
                            
                                3.6. Maximum Block Depth Configuration
                            
                        
                            
                            
                                3.7. Clocking Modes and Clock Enable
                            
                        
                            
                            
                                3.8. Memory Blocks Address Clock Enable Support
                            
                        
                            
                            
                                3.9. Byte Enable
                            
                        
                            
                            
                                3.10. Asynchronous Clear
                            
                        
                            
                            
                                3.11. Read Enable
                            
                        
                            
                                3.12. Read-During-Write
                            
                            
                        
                            
                            
                                3.13. Power-Up Conditions and Memory Initialization
                            
                        
                            
                            
                                3.14. Error Correction Code
                            
                        
                            
                            
                                3.15. Freeze Logic
                            
                        
                    
                5. Parameters and Signals
Section Content
RAM: 1-Port IP Core Parameters
RAM: 2-Port IP Core Parameters
ROM: 1-PORT IP Core Parameters
ROM: 2-PORT IP Core Parameters
Signals
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