Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

Download PDF
ID 683240
Date 9/17/2021
Public
Document Table of Contents
Document Table of Contents x
1. About Embedded Memory IP Cores 2. Embedded Memory IP Cores Getting Started 3. Functional Description 4. Embedded Memory Design Consideration 5. Parameters and Signals 6. Design Example 7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
1. About Embedded Memory IP Cores x
1.1. Features
2. Embedded Memory IP Cores Getting Started x
2.1. Changing Parameter Settings Manually 2.2. RAM and ROM Parameter Settings
3. Functional Description x
3.1. Memory Block Types 3.2. Write and Read Operations Triggering 3.3. Port Width Configurations 3.4. Mixed-width Port Configuration 3.5. Mixed-width Ratio Configuration 3.6. Maximum Block Depth Configuration 3.7. Clocking Modes and Clock Enable 3.8. Memory Blocks Address Clock Enable Support 3.9. Byte Enable 3.10. Asynchronous Clear 3.11. Read Enable 3.12. Read-During-Write 3.13. Power-Up Conditions and Memory Initialization 3.14. Error Correction Code 3.15. Freeze Logic
3.12. Read-During-Write x
3.12.1. Selecting RDW Output Choices for Various Memory Blocks
4. Embedded Memory Design Consideration x
4.1. Avoid Providing Non-Deterministic Input
5. Parameters and Signals x
5.1. RAM: 1-Port IP Core Parameters 5.2. RAM: 2-Port IP Core Parameters 5.3. ROM: 1-PORT IP Core Parameters 5.4. ROM: 2-PORT IP Core Parameters 5.5. Signals
6. Design Example x
6.1. External ECC Implementation with True-Dual-Port RAM
6.1. External ECC Implementation with True-Dual-Port RAM x
6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core 6.1.2. Simulating the Design
6.1.2. Simulating the Design x
6.1.2.1. Simulation Results
1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

5.4. ROM: 2-PORT IP Core Parameters

This table lists the ROM: 2-PORT IP Core parameters.
Table 19.  ROM: 2-PORT IP Core Parameters
Parameter Legal Values Description
Parameter Settings: Widths/Blk Type
How do you want to specify the memory size?
  • As a number of words
  • As a number of bits
 Determines whether to specify the memory size in words or bits.
How many <X>-bit words of memory? 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 Specifies the number of <X>-bit words.
Use different data widths on different ports On/Off Specifies whether to use different data widths on different ports.
How wide should the ‘q_a’ output bus be? — Specifies the width of the ‘q_a’ and ‘q_b’ output ports.
How wide should the ‘q_b’ output bus be?
What should the memory block type be? Auto, M4K, M9K, M144K, M10K, M20K Specifies the memory block type. The types of memory block that are available for selection depends on your target device
Set the maximum block depth to Auto, 128, 256, 512, 1024, 2048, 4096 Specifies the maximum block depth in words. This option is enabled only when you choose Auto as the memory block type.
Parameter Settings: Clks/Rd, Byte En
What clocking method would you like to use?
  • Single clock
  • Dual clock: use separate ‘input’ and ‘output’ clocks
  • Dual clock: use separate clocks for A and B ports

Specifies the clocking method to use.

  • Single clock—A single clock and a clock enable controls all registers of the memory block
  • Dual clock: use separate ‘input’ and ‘output’ clocks—The input clock controls the address registers and the output clock controls the data-out registers. There are no write-enable, byte-enable, or data-in registers in ROM mode.
  • Dual clock: use separate clocks for A and B ports—Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
Create a ‘rden_a’ and ‘rden_b’ read enable signals — Specifies whether to create read enable signals.
Parameter Settings: Regs/Clkens/Aclrs
Read output port(s) ‘q_a’ and ‘q_b’ On/Off Specifies whether to register the ‘q_a’ and ‘q_b’ output ports.
More Options ‘q_a’ port On/Off Specifies whether to register the ‘q_a’ output port.
‘q_b’ port On/Off Specifies whether to register the ‘q_b’ output port.
Create one clock enable signal for each clock signal. On/Off Specifies whether to turn on the option to create one clock enable signal for each clock signal.
More Options Use clock enable for port A input registers On/Off Specifies whether to use clock enable for port A input registers.
Use clock enable for port A output registers On/Off Specifies whether to use clock enable for port A output registers.
Create an ‘addressstall_a’ input port. On/Off Specifies whether to create addressstall_a and addressstall_b input ports. You can create these ports to act as an extra active low clock enable input for the address registers.
Create an ‘addressstall_b’ input port. On/Off Specifies whether to create an asynchronous clear port for the registered ports.
Create an ‘aclr’ asynchronous clear for the registered ports. On/Off Specifies whether to create an asynchronous clear port for the registered ports.
More Options ‘q_a’ port On/Off Specifies whether the ‘q_a’ port should be cleared by the aclr port.
‘q_b’ port On/Off Specifies whether the ‘q_b’ port should be cleared by the aclr port.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory? Yes, use this file for the memory content data

Specifies the initial content of the memory.

In ROM mode you must specify a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex).

The Yes, use this file for the memory content data option is turned on by default.

The initial content file should conform to which port’s dimensions?
  • PORT_A
  • PORT_B
 Specifies whether the initial content file conforms to port A or port B.
Level Two Title