1.3.5. Avoiding Simulation Node Name Match
Node name mismatches happen when you have .vcd applied to entities other than the top-level entity. In a modular design flow, the gate-level simulation files created in different Intel® Quartus® Prime projects might not match their node names with the current Intel® Quartus® Prime project.
For example, you may have a file named 8b10b_enc.vcd, which the Intel® Quartus® Prime software generates in a separate project called 8b10b_enc while simulating the 8b10b encoder. If you import the .vcd into another project called Top, you might encounter name mismatches when applying the .vcd to the 8b10b_enc module in the Top project. This mismatch happens because the Intel® Quartus® Prime software might name all the combinational nodes in the 8b10b_enc.vcd differently than in the Top project. To avoid such mismatches, Intel® recommends using .vcd files generated from simulation of your top level project.
Did you find the information on this page useful?