Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 6/22/2022
Public
Document Table of Contents

2.4.1.1.3. I/O PLL Clock Gate

You can dynamically gate each of the device's I/O PLL output counters, using I/O PLL Reconfiguration.

Refer to the I/O PLL Clock Gate section of the Clocking and PLL User Guide for your Intel® device.

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