Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 6/22/2022
Public
Document Table of Contents

2.4.1.1.1. Root Clock Gate

You can gate each clock network dynamically at the root level, using the Clock Control Intel FPGA IP Core.

Refer to the Root Clock Gate section of the Clocking and PLL User Guide for your Intel® device.

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