Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 6/22/2022
Public
Document Table of Contents

2.4.1.1. Clock Gating

For designs containing logic that is not operational 100% of the time, you can reduce power consumption by gating (disabling) the clock that feeds that logic.

This solution requires that the logic in question have its own dedicated clock source. Clock duplication (such as introducing a duplicate PLL clock output) is necessary if the logic in question does not have its own dedicated clock source.

The following topics describe methods for gating clock networks.

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