Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

Download PDF
ID 683148
Date 6/19/2017
Public
Document Table of Contents
Document Table of Contents x
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide x
1.1. ALTDDIO Features 1.2. ALTDDIO Common Applications 1.3. ALTDDIO Resource Utilization and Performance 1.4. ALTDDIO Parameter Settings 1.5. ALTDDIO Functional Description 1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR 1.7. ALTDDIO_IN IP Core Signals 1.8. ALTDDIO_OUT IP Core Signals 1.9. ALTDDIO_BIDIR IP Core Signals 1.10. Verilog HDL Prototype 1.11. VHDL Component Declaration 1.12. VHDL LIBRARY-USE Declaration 1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives 1.14. Document Revision History
1.2. ALTDDIO Common Applications x
1.2.1. DDR SDRAM, DDR2 SDRAM and RLDRAM II Memory 1.2.2. QDR SRAM and QDRII SRAM Memory Interfaces 1.2.3. High-Speed Interface Applications
1.5. ALTDDIO Functional Description x
1.5.1. DDR Device Configuration 1.5.2. DDR I/O Timing
1.5.1. DDR Device Configuration x
1.5.1.1. Input Configuration 1.5.1.2. Output Configuration 1.5.1.3. Bidirectional Configuration
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR x
1.6.1. Generate a Divider Using ALTDDIO_BIDIR 1.6.2. Create a Divider 1.6.3. Implement the Divider Design 1.6.4. Functional Results—Simulate the Divider Design in the ModelSim* - Intel® FPGA Edition Software
1.6.1. Generate a Divider Using ALTDDIO_BIDIR x
1.6.1.1. Create the ALTDDIO_BIDIR IP Core 1.6.1.2. Create the LPM_DIVIDE IP core
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

1.8. ALTDDIO_OUT IP Core Signals

This figure shows the ports for the ALTDDIO_OUT IP core.
Figure 10.  ALTDDIO_OUT Signals

These tables list the input and output ports for the ALTDDIO_OUT IP core.

Table 6.   ALTDDIO_OUT Input Ports
Name Required Description
datain_h[] Yes Input data for rising edge of outclock port. Input port WIDTH wide.
datain_l[] Yes Input data for falling edge of outclock port. Input port WIDTH wide.
outclock Yes Clock signal to register data output. dataout port outputs DDR data on each level of outclock signal.
outclocken No Clock enable for outclock port.
aclr No Asynchronous clear input. The aclr and aset ports cannot be connected at the same time.
aset No Asynchronous set input. The aclr and aset ports cannot be connected at the same time.
oe No Output enable for the dataout port. Active-high signal. You can add an inverter if you need an active-low oe.
sclr No Synchronous clear input. The sclr and sset ports cannot be connected at the same time. The sclr port is available for Arria®  GX, Stratix®  III, Stratix®  II, Stratix®  II GX, Stratix® , Stratix®  GX, HardCopy II, and HardCopy  Stratix® devices only.
sset No Synchronous set input. The sclr and sset ports cannot be connected at the same time. The sset port is available for Arria®  GX, Stratix®  III, Stratix®  II, Stratix®  II GX, Stratix® , Stratix®  GX, HardCopy II, and HardCopy  Stratix® devices only.
Table 7.   ALTDDIO_OUT Output Ports
Name Required Description
dataout[] Yes DDR output data port. Output port WIDTH wide. dataout port should directly feed an output pin in top-level design.
oe_out No Output enable for the bidirectional padio port. Output port [WIDTH–1..0] wide. This port is available for Stratix®  III and Cyclone®  III devices only.
Level Two Title