Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

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ID 683148
Date 6/19/2017
Public
Document Table of Contents
Document Table of Contents x
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide x
1.1. ALTDDIO Features 1.2. ALTDDIO Common Applications 1.3. ALTDDIO Resource Utilization and Performance 1.4. ALTDDIO Parameter Settings 1.5. ALTDDIO Functional Description 1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR 1.7. ALTDDIO_IN IP Core Signals 1.8. ALTDDIO_OUT IP Core Signals 1.9. ALTDDIO_BIDIR IP Core Signals 1.10. Verilog HDL Prototype 1.11. VHDL Component Declaration 1.12. VHDL LIBRARY-USE Declaration 1.13. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Archives 1.14. Document Revision History
1.2. ALTDDIO Common Applications x
1.2.1. DDR SDRAM, DDR2 SDRAM and RLDRAM II Memory 1.2.2. QDR SRAM and QDRII SRAM Memory Interfaces 1.2.3. High-Speed Interface Applications
1.5. ALTDDIO Functional Description x
1.5.1. DDR Device Configuration 1.5.2. DDR I/O Timing
1.5.1. DDR Device Configuration x
1.5.1.1. Input Configuration 1.5.1.2. Output Configuration 1.5.1.3. Bidirectional Configuration
1.6. Design Example: 8-Bit DDR Divider Using ALTDDIO_BIDIR x
1.6.1. Generate a Divider Using ALTDDIO_BIDIR 1.6.2. Create a Divider 1.6.3. Implement the Divider Design 1.6.4. Functional Results—Simulate the Divider Design in the ModelSim* - Intel® FPGA Edition Software
1.6.1. Generate a Divider Using ALTDDIO_BIDIR x
1.6.1.1. Create the ALTDDIO_BIDIR IP Core 1.6.1.2. Create the LPM_DIVIDE IP core
1. Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

1.14. Document Revision History

The following table lists the revision history for this document.
Table 11.  Document Revision History
Date Version Changes
June 2017 2017.06.19
  • Added the Intel® Cyclone® 10 LP device family.
  • Updated title of design example section.
  • Renamed "MegaWizard Plug-In Manager" to "parameter editor" or "IP catalog".
  • Renamed "megafunction" and "module" to "IP core".
  • Renamed "Quartus II" to "Quartus Prime".
  • Renamed "ModelSim-Altera" to "Modelsim - Intel FPGA Edition"
  • Updated the steps to create the IP core variations.
July 2015 2015.07.02 Updated Arria V, Cyclone V and Stratix V as supported devices.
January 2015 2015.01.23 Added link to design example file.
December 2014 2014.12.15 Template update.
January 2013 6.1 Updated to correct content error in “DDR I/O Timing” on page 3–7.
February 2012 6.0 Updated to refelect new GUI changes.
September 2010 5.0 Added ports and parameters.
June 2007 4.2 Updated for Quartus II software version 7.1:
  • Updated for Arria GX and Cyclone III devices.
  • Updated and renamed “DDR MegaWizard Plug-Ins Page Descriptions” section.
  • Added parameter to the ALTDDIO_IN megafunction.
  • Added “Referenced Documents” section.

    Updated “Revision History” and “How to Contact Altera” sections.
March 2007 4.1 Added Cyclone III device to list of supported devices.
July 2006 4.0 Updated to reflect Quartus II 6.0 release, added ModelSim simulation information, updated design examples.
March 2005 3.0 Updated to reflect new GUI changes.
December 2004 2.0 Updated to reflect new document organization and GUI changes.
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