Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide

ID 683148
Date 6/19/2017
Public
Document Table of Contents

1.9. ALTDDIO_BIDIR IP Core Signals

This figure shows the ports for the ALTDDIO_BIDIR IP core.
Figure 11. ALTDDIO_BIDIR Ports

These tables list the output ports and the bidirectional ports for the ALTDDIO_BIDIR IP core.

Table 8.  ALTDDIO_BIDIR Input Ports
Name Required Description
datain_h[] Yes Input data to be output to the padio port at the rising edge of the outclock port. Input port [(WIDTH) - (1)..0] wide.
datain_l[] Yes Input data to be output to the padio port at the falling edge of the outclock port. Input port [(WIDTH) - (1)..0] wide.
inclock Yes Clock signal to sample the DDR input. The padio port is sampled on each clock edge of the inclock signal.
inclocken No Clock enable for the inclock port.
outclock Yes Clock signal to register the data output. The padio port outputs the DDR data on each edge of the outclock signal.
outclocken No Clock enable for the outclock port.
aclr No Asynchronous clear input. The aclr and aset ports cannot be connected at the same time.
aset No Asynchronous set input. The aclr and aset ports cannot be connected at the same time.
oe No Output enable for the bidirectional padio port. If the oe port is not connected, then the padio port is an output port.
sclr No Synchronous clear input. The sclr and sset ports cannot be connected at the same time. The sclr port is available for Arria®  GX, Stratix®  III, Stratix®  II, Stratix®  II GX, Stratix® , Stratix®  GX, HardCopy II, and HardCopy  Stratix® devices only. 2
sset No Synchronous set input. The sclr and sset ports cannot be connected at the same time. The sset port is available for Arria®  GX, Stratix®  III, Stratix®  II, Stratix®  II GX, Stratix® , Stratix®  GX, HardCopy II, and HardCopy  Stratix® devices only. 2
Table 9.  ALTDDIO_BIDIR Output Ports
Name Required Description
dataout_h[] Yes Data sampled from the padio port at the rising edge of the inclock signal. Output port [WIDTH–1..0] wide.
dataout_l[] Yes Data sampled from the padio port at the falling edge of the inclock signal. Output port [WIDTH-1..0] wide.
combout[](1) No Combinational output directly fed by the padio port. 3
dqsundelayedout[] No Undelayed output from the DQS pins. Output port [WIDTH-1..0] wide. 4
oe_out No Output enable for the bidirectional padio port. Output port [WIDTH–1..0] wide. This port is available for Stratix®  III and Cyclone®  III devices only.
Table 10.  ALTDDIO_BIDIR Bidirectional Port
Name Required Description
padio[] Yes Bidirectional DDR port that should directly feed a bidirectional pin in the top-level design. The DDR data is transmitted and received on this bidirectional port. Bidirectional port [(WIDTH) - (1)..0] wide.
2 When designing with Stratix®  III devices, when sclr is deasserted, it synchronously presents both the input path and resynchronization register.
3 This port is available for Stratix® series, HardCopy Stratix® , Cyclone® series, and APEX II devices only.
4 This port is available for Stratix® and HardCopy Stratix® devices only.

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