184.108.40.206. Step 4: Plan Periphery Placement
For efficiency, place design elements in the following order in Interface Planner:
- Place all I/O pins or elements, such as PLLs, that have known, specific location requirements.
- Place all known periphery interface IP.
- (Optional) Place all remaining unplaced cells.
Use the following controls to place design elements in the Interface Planner floorplan:
- Locate design elements that you want to place in the Design Element list. You can search and filter the list by name, IP, placement status, I/Os, and other criteria.
- To customize design element color coding definitions, click the Highlight column.
Figure 12. Interface Planner (Plan Tab)
- Use any of the following methods to place design elements in the floorplan:
Figure 13. Listing Legal Locations
- Drag elements from the Design Elements list and drop them onto available device resources in the Chip or Package view. Use Ctrl+Click to drag and pan across the Chip or Package views. You may experience a small delay while dragging as Interface Planner calculates the legal locations.
- To allow Interface Planner to place an unplaced design element in a legal location, right-click and select Autoplace Selected. You must use Autoplace Selected for all unplaced clocks .
- Click the button next to the Design Elements to display a list of Legal Locations. Click any legal location in the list to highlight the location in the floorplan. Double-click any location in the list to place the element in the location.
- To step forward and backward though your plan changes, click the Undo and Redo buttons.
- To visualize and traverse design connectivity (for example, to view the reference clock pin and driven destination cells of a PLL), select any design element and then click the Link Info tab. Click the Back and Forward buttons to traverse design connectivity.
- To generate a report that shows the placement locations the Fitter prefers, select a design element and click Report Placeability of Selected Element.
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