22.214.171.124. Specify Instance-Specific Constraints in Assignment Editor 126.96.36.199. Specifying Multi-Dimensional Bus Constraints 188.8.131.52. Specify I/O Constraints in Pin Planner 184.108.40.206. Plan Interface Constraints in Interface Planner and Tile Interface Planner 220.127.116.11. Adjust Constraints with the Chip Planner 18.104.22.168. Constraining Designs with the Design Partition Planner
1. Constraining Designs
|Intel® Quartus® Prime Design Suite 22.1|
The design constraints, assignments, and logic options that you specify influence how the Intel® Quartus® Prime Compiler implements your design. The Compiler attempts to synthesize and place logic in a manner than meets your constraints. In addition, design constraints also have an impact on how the Timing Analyzer and the Power Analyzer influence synthesis, placement, and routing.
You can specify design constraints in the GUI, with scripts, or directly in the files that store the constraints. The Intel® Quartus® Prime software preserves the constraints that you specify in the GUI in the following files:
- Intel® Quartus® Prime Settings file (<project_directory>/<revision_name>.qsf)—contains project-wide and instance-level assignments for the current revision of the project, in Tcl syntax. Each revision of a project has a separate .qsf file.
- Synopsys* Design Constraints file (<project_directory>/<revision_name>.sdc)—the Timing Analyzer uses industry-standard Synopsys* Design Constraint format and stores those constraints in .sdc files.