Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/27/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.2.6. Step 6: Run Logic Generation and Design Synthesis

After saving your tile plan assignments, run the Compiler's Logic Generation stage to implement your tile plan and continue synthesis and the remaining design compilation stages.
To run Logic Generation and design synthesis, follow these steps:
  1. Save your tile interface plan, as Step 5: Save Tile Plan Assignments describes.
  2. In the Intel® Quartus® Prime software, double-click the Logic Generation stage in the Compilation Dashboard. Logic Generation reads the tile plan assignments from the .qsf.
    Figure 41. Run Logic Generation Stage Before Synthesis
  3. When Logic Generation is complete, double-click Analysis & Synthesis on the Compilation Dashboard.
  4. When Analysis & Synthesis is complete, you can run the other remaining downstream stages in the compilation flow when ready.

Did you find the information on this page useful?

Characters remaining:

Feedback Message