184.108.40.206. Specify Instance-Specific Constraints in Assignment Editor 220.127.116.11. Specifying Multi-Dimensional Bus Constraints 18.104.22.168. Specify I/O Constraints in Pin Planner 22.214.171.124. Plan Interface Constraints in Interface Planner and Tile Interface Planner 126.96.36.199. Adjust Constraints with the Chip Planner 188.8.131.52. Constraining Designs with the Design Partition Planner
184.108.40.206. Plan Tab Controls
The Plan tab contains the following controls to help you locate and place logic in the interface plan. Click Plan Design to display the Plan tab.
Placement or unplacement in the interface plan does not apply to your Intel® Quartus® Prime project until you add the generated Interface Planner constraints script to your project.
|Lists legal locations for placement.
|Display a list of Intel® Quartus® Prime Pro Edition tools where the selected design element is referenced in the hierarchical database. If the Locate Node command is disabled for a specific element in the Design Elements list, it is because that element is not represented as an element in the design.
|Attempts to place all unplaced design elements in legal locations in the interface plan.
|Attempts to place all unplaced design elements that have only one legal location into the interface plan.
|Unplaces all placed design elements in the interface plan.
|Right-click > Auto-place selected element
|Attempts to place the selected design element and all its children in a legal location in the interface plan.
|Displays the target device chip. Zoom in to display chip details.
|Displays the target device package. Zoom in to display chip details.
|Show I/O Banks
|Selects and color codes the I/O banks in the Plan tab.
|Show Differential Pin Pair Connections
|In Package View, displays a red connection line between a pair of differential pins. The Package View labels the positive and negative pins with the letters p and n, respectively.
|Show PCIe Hard IP Interface Pins
|In Package View, selects and color codes the PCIe Hard IP interface pins in the Plan tab. To access this command, right-click in the Plan tab package view, and select x1 Lanes, x2 Lanes, x4 Lanes, x8 Lanes, or by 16 Lanes. After enabling, view color coding in the Color Legend.
|Show DQ/DQS Pins
|In Package View, selects and color codes the PCIe Hard IP interface pins in the Plan tab. To access this command, right-click in the Plan tab package view, and select x4 Mode, x8/x9 Mode, x16/x16 Mode, or x32/x36 Mode. After enabling, view color coding in the Color Legend.
|Right-click > Report Placeability of Selected Element
|After selecting a low level element, displays detailed information on the Reports tab, showing legal locations in the interface plan for the selected cell in order of suitability for fitting.
|Right-click > Report Legal Locations of Selected Element
|After selecting a low level element, displays the legal locations in the interface plan for the selected cell in order of suitability for fitting.
|Copies the current interface plan to the clipboard for pasting into other files, such as word processing or presentation files.
|Unplaces all placed design elements and removes applied project assignments from the interface plan. Resets all project assignments to the enabled state. You must subsequently run Update Plan prior to placing design elements. This command only applies to your interface plan and does not impact your Intel® Quartus® Prime project assignments until you apply the Interface Planner script.
|Allows you to select and load an Interface Planner Floorplan Format (.plan) file. You can save Interface Planner floorplan files in the format by clicking Save Floorplan.
|Allows you to save your Interface Planner floorplan as a .plan file.