Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/27/2022
Public

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2.2. Using Tile Interface Planner

The Intel® Quartus® Prime Tile Interface Planner helps you to quickly place component IP in legal tile locations of device F-tiles. Tile Interface Planner is an interactive floorplanning tool that simplifies this process.

Tile Interface Planner displays your project's component IP in a hierarchical tree view, next to a visual representation of the device tile segments. You can then locate the potential legal locations for each IP within the tile, place each IP at one of these locations, and apply generated placement constraints to the project for downstream Compiler stages.

As you place elements in the tile floorplan, the legality engine verifies that the placement is legal in real-time, thus ensuring correlation with your intent in the final implementation.

Figure 24. Tile Interface Planner GUI

In contrast with Interface Planner, Tile Interface Planner is specifically for placing component IP on the F-tile, and requires you to run an initial Design Analysis stage before you define a legal tile floorplan for all component IP targeting device tiles.

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