Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 4/27/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.1.2.5. Adjust Constraints with the Chip Planner

With the Chip Planner you can adjust existing assignments to device resources, such as pins, logic cells, and LABs in a graphical representation of the device floorplan. You can also view equations and routing information and demote assignments by dragging and dropping to Logic Lock regions in the Logic Lock Regions Window.

Figure 4. Chip Planner GUI

Did you find the information on this page useful?

Characters remaining:

Feedback Message