SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/09/2024
Document Table of Contents

7.1.3. Handling Transceiver in Agilex™ 7 F-Tile Devices

F-Tile PMA/FEC Direct PHY Intel FPGA IP supports two clocking modes: the System PLL Clocking Mode and the Traditional PMA Clocking Mode.

Note: If you need to dynamically reconfigure the PHY, only System PLL clocking mode is supported.