SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/09/2024
Document Table of Contents

7.2. Timing Violation

You may avoid some timing violation for Arria V, Cyclone V, and Stratix V designs by editing .qsf.
After you create a new project, the Quartus® Prime software generates a .qsf. Add the following assignments to the .qsf file to avoid timing violation from the synchronizers.
set_instance_assignment -name GLOBAL_SIGNAL OFF -to *|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out