SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/09/2024
Document Table of Contents

5.2. Transceiver

The transceiver block consists of two components:
  • PHY management and adapter
  • Native PHY IP
These two components handle the serial transport aspects of the SDI II IP core.
Note: The transceiver block is only available for Arria V, Cyclone V, and Stratix V devices. For Arria® 10, Cyclone® 10 GX, Stratix® 10 and Agilex™ 7 F-Tile devices, you must generate the transceiver and/or the TX PLL instances separately; refer to SDI Presets in the Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP and L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 IP Cores.

For Arria V, Cyclone V, and Stratix V devices, the SDI II IP core instantiates the Native PHY IP core using the Tcl file associated with each device.

The block diagram below illustrates the Native PHY IP core setup in the SDI II IP core (duplex) data path.

Figure 19. Native PHY IP Core Setup in Duplex ModeThe Native PHY IP core does not include an embedded reset controller and an Avalon® memory-mapped interface. This PHY IP core exposes all signals directly as ports. To implement reset functionality for a new IP core, the transceiver reset controller is required to handle all the transceiver reset sequencing. The transceiver reset controller controls the embedded reset controller and also manages additional control options such as automatic or manual reset recovery mode.