SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/09/2024
Document Table of Contents

3.3. SDI II IP Core Component Files

Table 11.  Generated FilesTable below describes the generated files and other files that might be in your project directory. The names and types of files vary depending on whether you create your design with VHDL or Verilog HDL.



<variation name>.sv

An IP core variation file, which defines a Verilog HDL description of the custom IP core. Instantiate the entity defined by this file inside your design.

<variation name>.v (Arria V, Cyclone V, and Stratix V devices)

<variation name>.qsys (

Arria® 10 on Quartus® Prime Standard Edition )
<variation name>.ip

( Quartus® Prime Pro Edition )

<variation name>.sdc

Contains timing constraints for your SDI variation.

<variation name>.qip

Contains Quartus® Prime project information for your IP core variations. Add this file in your Quartus® Prime project before you compile your design in the Quartus® Prime software.