SDI II Intel® FPGA IP User Guide

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ID 683133
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices 5.4.6. Intel FPGA Video Streaming Interface
5.4.6. Intel FPGA Video Streaming Interface x
5.4.6.1. RGB Pixel Packing 5.4.6.2. YCbCr 444 Pixel Packing 5.4.6.3. YCbCr 422 Pixel Packing 5.4.6.4. Supported Modes
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation 7.3. SDI II IP Core Registers
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Arria® 10, Cyclone® 10 GX, and Stratix® 10 Devices 7.1.3. Handling Transceiver in Agilex™ 7 F-Tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Arria® 10, Cyclone® 10 GX, and Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Arria® 10 and Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Arria® 10 and Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Stratix® 10 Devices
7.1.3. Handling Transceiver in Agilex™ 7 F-Tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Transceiver Settings 7.1.3.3. TX Transceiver Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. SmartVID Settings 7.1.3.6. Dynamic Reconfiguration 7.1.3.7. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.1.3.2. RX Transceiver Settings x
7.1.3.2.1. Multi-rate Designs 7.1.3.2.2. Triple-rate Designs 7.1.3.2.3. Single-rate Designs
7.3. SDI II IP Core Registers x
7.3.1. SDI II Tx Register Summary 7.3.2. SDI II Tx Register Description 7.3.3. SDI II Rx Register Summary 7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.1. Design Examples for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile Devices x
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon® Memory-Mapped Interface Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II Intel® FPGA IP Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

6.1. SDI II IP Core Resets and Clocks

Table 18.  Resets and Clock Signals
Signal Width Direction Description
tx_rst 1 Input

Reset signal for the transmitter. This signal is active high and level sensitive.

This signal must be synchronous to tx_pclk clock domain (for Agilex™ 7 F-Tile, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices). Not applicable for for Arria V, Cyclone V, and Stratix V devices.

pll_powerdown_in 1N Input

When asserted, this signal resets TX PLL. You must connect this signal to pll_powerdown_out.

You can connect this signal from multiple SDI instances to pll_powerdown_out of one of the SDI instances to merge the PLL in these instances.

For TX PLL merging, pll_powerdown_in and xcvr_refclk from multiple instances must share the same source.

N = Number of PLLs in the core—1 (default) or 2 (when TX PLL switching enabled)

Note: Not applicable for these settings:
  • In protocol only mode.
  • For Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile devices.

If you enabled the Dynamic Tx clock switching parameter, your design requires XCVR_TX_PLL_RECONFIG_GROUP QSF assignment. Refer to the Transceiver PHY IP Core User Guide for more information.

pll_powerdown_out 1N Output

When asserted, this signal resets the selected TX PLL.

N = Number of PLLs in the core—1 (default) or 2 (when TX PLL switching enabled)

Note: Not applicable for these settings:
  • In protocol only mode.
  • For Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile devices.
rx_rst 1 Input

Reset signal for the receiver. This signal is active high and level sensitive. This reset signal must be synchronous to the rx_coreclk or rx_coreclk_hd clock domain.

rx_rst_proto_in 1 Input
Receiver protocol reset signal. This signal must be driven by the rx_rst_proto_out reset signal from the transceiver block.
Note: Applicable for receiver protocol configuration only (Arria V, Cyclone V, and Stratix V devices).
rx_rst_proto_in_b 1 Input
Receiver protocol reset signal for link B. This signal must be driven by the rx_rst_proto_out_b reset signal from the transceiver block.
Note: For HD-SDI dual link receiver protocol configuration only.
rx_rst_proto_out 1 Output

Reset the receiver protocol downstream logic. This generated signal is synchronous to rx_clkout clock domain and must be used to drive the rx_rst_proto_in signal of the receiver protocol block.

rx_rst_proto_out_b

1

Output
Reset the receiver protocol downstream logic.
Note: For HD-SDI dual link receiver transceiver configuration only.
trig_rst_ctrl 1 Output Reset output signal to the transceiver reset controller to reset the transceiver. This signal is synchronous to the rx_coreclk or rx_coreclk_hd clock domain.
Note: Applicable only for Agilex™ 7 F-Tile, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices.
tx_axi4s_reset 3 1 Input Tx AXI4-Stream reset.
rx_axi4s_reset 3 1 Input Rx AXI4-Stream reset.
tx_pclk 1 Input

Transmitter core parallel clock signal. This clock signal must be driven by the by parallel output clock from TX transceiver.

  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • HD-SDI Dual Link = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • Dual Rate = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • Triple Rate = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • Multi Rate (up to 12G-SDI) = 148.5 MHz or 148.35 MHz, depending on video frame rate
tx_coreclk 1 Input

148.5-MHz or 148.35-MHz transmitter core clock signal. This clock source must be always stable and can be shared with xcvr_refclk.

Note: Not applicable for the following settings:
  • In protocol only mode.
  • If the selected transceiver reference clock frequency is 74.25 MHz/74.175 MHz.
  • For Agilex™ 7 F-Tile, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices.
tx_coreclk_hd 1 Input

74.25-MHz or 74.175-MHz transmitter core clock signal. This clock source must be always stable and can be shared with xcvr_refclk.

Note: Applicable for HD-SDI and HD-SDI dual link modes only if the selected transceiver reference clock frequency is 74.25 MHz/74.175 MHz. Not applicable for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile devices.
rx_coreclk 1 Input
Receiver core clock signal. You can set the following frequencies:
  • 148.5-MHz or 148.35-MHz: Applicable for all configurations.
  • 297.0 MHz or 296.70 MHz: Applicable only for Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices in multi-rate modes.
Note: For the Agilex™ 7 device, set the clock frequency range between 100 MHz to 156.25 MHz. Intel recommends sharing the same clock as the i_csr_clk port from the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP core.

This clock source must be stable and there are no required relationships with any other clocks. The clock source can be asynchronous or synchronous to any transceiver's clock.

Note: Not applicable if the selected transceiver reference clock frequency is 74.25 MHz/74.175 MHz.
For Stratix® 10 devices, assign this clock to a GPIO clock instead of a transceiver reference clock pin if the following conditions apply:
  • Uses channel 0 and channel 3 in a transceiver bank.
  • SDI RX and TX cores are placed in either one of these channels.
  • Both SDI RX and RX cores are in multi-rate mode.
rx_coreclk_hd 1 Input

74.25-MHz or 74.175-MHz receiver core clock signal. This clock source must be always stable and can be shared with xcvr_refclk.

This clock source must be stable and there are no required relationships with any other clocks. The clock source can be asynchronous or synchronous to any transceiver's clock.

Note: Applicable for HD-SDI and HD-SDI dual link modes only if the selected transceiver reference clock frequency is 74.25 MHz/74.175 MHz. Not applicable for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile devices.
rx_clkin 1 Input
Receiver protocol clock input. This signal must be driven by the rx_clkout clock signal from the transceiver block.
  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
Note: For receiver protocol configuration only. Not applicable for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile devices.
rx_clkin_b 1 Input
Receiver protocol clock input for link B. This signal must be driven by the rx_clkout_b clock signal from the transceiver block ((74.25 MHz or 74.125 MHz, depending on video frame rate).
Note: For HD-SDI dual link receiver protocol configuration only. Not applicable for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile devices.
rx_clkin_smpte372 1 Input

Clock input for HD-SDI dual link to 3G-SDI (level B) and 3G-SDI (level B) to HD-SDI dual link operations.

  • HD-SDI dual link to 3G-SDI (level B) = 148.5 MHz or 148.35 MHz
  • 3G-SDI (level B) to HD-SDI dual link = 74.25 MHz or 74.175 MHz
xcvr_rxclk 1 Input

Receiver parallel clock input. Driven by rx_pma_div_clkout (for multi-rate modes) or rx_clkout (for other modes) from the transceiver.

  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • 6G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • 12G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
Note: Applicable only for Agilex™ 7 F-Tile, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices.
xcvr_refclk 1 Input

Reference clock signal for the transceiver. Only a single reference clock frequency is required to support both integer and fractional frame rates for RX CDR.

The clock source must be stable. It must be a free running clock connected to the transceiver clock pin.

  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz, 74.175 MHz, 148.5 MHz, or 148.35 MHz
  • 3G-SDI = 148.5 MHz or 148.35 MHz
  • HD-SDI Dual Link: 74.25 MHz, 74.175 MHz, 148.5 MHz, or 148.35 MHz
  • Dual Rate: 148.5 MHz or 148.35 MHz
  • Triple Rate: 148.5 MHz or 148.35 MHz
Note: Not applicable for Agilex™ 7 F-Tile, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices.
xcvr_refclk_alt 1 Input

Alternative clock input for the Native PHY IP core. The frequency of this signal must be the alternate frequency value of the xcvr_refclk signal.

  • HD-SDI = 74.25 MHz, 74.175 MHz, 148.5 MHz, or 148.35 MHz
  • 3G-SDI = 148.5 MHz or 148.35 MHz
  • HD-SDI Dual Link: 74.25 MHz, 74.175 MHz, 148.5 MHz, or 148.35 MHz
  • Dual Rate: 148.5 MHz or 148.35 MHz
  • Triple Rate: 148.5 MHz or 148.35 MHz
Note: Applicable only when you turn on the Tx PLL Dynamic Switching option. Not applicable for Agilex™ 7 F-Tile, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices.
tx_axi4s_clk 3 1 Input TX AXI4-Stream clock.
rx_axi4s_clk 3 1 Input RX AXI4-Stream clock. 
mgmt_clk
3 		1 Input Clock for the Avalon memory-mapped control interface.
tx_clkout 1 Output

TX transceiver parallel output clock.

This frequency for this clock should be the same as the user-provided xcvr_refclk.

Note: Not applicable for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile devices.
rx_clkout 1 Output
RX transceiver parallel output clock.
  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
Note: Not applicable for Agilex™ 7 F-Tile, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices.
rx_clkout_b 1 Output

RX transceiver parallel output clock for link B. The output clock frequency must be 74.25 or 74.175 MHz, depending on video frame rate.

Note: For HD-SDI dual link only.
Figure 43. TX Clocking Diagram for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile Devices


Figure 44. RX Clocking Diagram for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile Devices


Note: For a more comprehensive TX and RX Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile clocking diagrams with transceivers, refer to the respective design example user guides.
Figure 45. TX Clocking Diagram for Arria V, Cyclone V, and Stratix V Devices


Figure 46. RX Clocking Diagram for Arria V, Cyclone V, and Stratix V Devices


Note: For the Arria V, Cyclone V, and Stratix V devices, the source or destination for dual link signals with "_b suffix are the same as the original signals. For example, the destination for rx_clkin_b is the same as rx_clkin. which is directed to the SDI RX protocol block. Similarly, the source of the output signal rx_rst_proto_out_b is the same as rx_rst_proto_out, which comes from the SDI RX PHY management block.
3 Only available when Enable active video data protocols = AXIS-VVP Full.
Level Two Title