SDI II Intel® FPGA IP User Guide

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ID 683133
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices 5.4.6. Intel FPGA Video Streaming Interface
5.4.6. Intel FPGA Video Streaming Interface x
5.4.6.1. RGB Pixel Packing 5.4.6.2. YCbCr 444 Pixel Packing 5.4.6.3. YCbCr 422 Pixel Packing 5.4.6.4. Supported Modes
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation 7.3. SDI II IP Core Registers
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Arria® 10, Cyclone® 10 GX, and Stratix® 10 Devices 7.1.3. Handling Transceiver in Agilex™ 7 F-Tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Arria® 10, Cyclone® 10 GX, and Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Arria® 10 and Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Arria® 10 and Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Stratix® 10 Devices
7.1.3. Handling Transceiver in Agilex™ 7 F-Tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Transceiver Settings 7.1.3.3. TX Transceiver Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. SmartVID Settings 7.1.3.6. Dynamic Reconfiguration 7.1.3.7. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.1.3.2. RX Transceiver Settings x
7.1.3.2.1. Multi-rate Designs 7.1.3.2.2. Triple-rate Designs 7.1.3.2.3. Single-rate Designs
7.3. SDI II IP Core Registers x
7.3.1. SDI II Tx Register Summary 7.3.2. SDI II Tx Register Description 7.3.3. SDI II Rx Register Summary 7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.1. Design Examples for Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 F-Tile Devices x
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon® Memory-Mapped Interface Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II Intel® FPGA IP Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

7.3.4. SDI II Rx Register Description

Table 55.  STATUS (0x50)
Name Bit(s) Access Description Reset
Reserved 31:12 - - -
Video locked 11 RO When asserted, indicates current signal value of the SDI frame locked signal. 0x0
Resolution valid 10 RO When asserted, indicates a valid resolution in the sample and line count registers. 0x0
Reserved 9 - - -
Stable 8 RO When asserted, the input video stream has had a consistent line length for two of the last three lines. 0x0
Interlaced 7 RO When asserted, the input video stream is interlaced. Otherwise, the input video stream is progressive. 0x0
Reserved 6:1 - - -
Status 0 RO This bit is asserted when the core is producing data 0x0
Table 56.  ACTIVE_SAMPLE_COUNT (0x52)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
Active sample count 15:0 RO The detected sample count of the video stream excluding blanking 0x0
Table 57.  F0_ACTIVE_LINE_COUNT (0x53)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 active line count 15:0 RO The detected line count of the interlaced video field 0 or progressive video excluding blanking. 0x0
Table 58.  F1_ACTIVE_LINE_COUNT (0x54)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F1 active line count 15:0 RO The detected line count of the interlaced video field 1 excluding blanking. 0x0
Table 59.  VIDEO_MODE_STANDARD (0x58)
Name Bit(s) Access Description Reset
Reserved 31:4 - - -
SDI mode 3 RO

This bit indicates the received video payload byte 1 bit 0 or the SDI mode for 6G-SDI and 12G-SDI.

0x1: 2081-10-2018 6G-SDI mode 2 and mode 3,

2082-10-2018 12G-SDI mode 2.

0x0: 2081-10-2018 6G-SDI mode 1,

2082-10-2018 12G-SDI mode 1 		0x0
SDI video standard 2:0 RO

The detected SDI video standard

0x0: SD-SDI

0x1: HD-SDI

0x2: 3G-SDI Level B

0x3: 3G-SDI Level A

0x4: 6G-SDI Level B

0x5: 6G-SDI Level A

0x7: 12G-SDI Level A 		0x0
Table 60.  COLOR_PATTERN (0x5C)
Name Bit(s) Access Description Reset
Reserved 31:13 - - -
Bit Depth 12:10 RO

The detected bit depth of each color sample.

3’d2: 10 bits

3’d4: 12 bits

 
Reserved 9 - - -
Chroma sub-sampling 8:7 RO

The detected chroma sub-sampling.

2’d0: 420

2’d2: 422

2’d3: 444

0x0
Reserved 6:1 - - -
Color space 0 RO

The detected color space.

1’d0: RGB

1’d1: YCbCr

 0x0
Table 61.  VPID_BYTE1 (0x5D)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 1 7:0 RW The detected video payload byte 1. 0x0
Table 62.  VPID_BYTE2 (0x5E)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 2 7:0 RW The detected video payload byte 2. 0x0
Table 63.  VPID_BYTE3 (0x5F)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 3 7:0 RW The detected video payload byte 3. 0x0
Table 64.  VPID_BYTE4 (0x60)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 4 7:0 RW The detected video payload byte 4. 0x0
Table 65.  CONTROL (0x64)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Go 0 WO Setting this bit to 1 causes the SDI II Rx core to start data output on the next video frame boundary. 0x0
Level Two Title