SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/09/2024
Document Table of Contents

3.2.4. Generating a Design Example and Simulation Testbench

After you have parameterized the SDI II IP core, click Generate Example Design to create the following entities:

  • Design example— serves as a common entity for simulation and hardware verification.
  • Simulation testbench—consists of the design example entity and other non-synthesizable components. The example testbench and the automated script are located in:
    • Arria V, Cyclone V, and Stratix V: <variation name>_example_design/sdi_ii/simulation/verilog

      or <variation name>_example_design/sdi_ii/simulation/vhdl directory.

    • Arria® 10, Cyclone® 10 GX, and Stratix® 10: <your design example folder>/simulation directory.
    • Agilex™ 7 F-Tile: <your design example folder>/simulation directory.
Note: Generating a design example can increase processing time.

You can now integrate your custom IP core variation into your design, simulate, and compile.