SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/05/2023
Public
Document Table of Contents

7.1.3.3. TX Transceiver Settings

TX EQ settings on the transceiver can be tuned as per your design requirement to get a better signal integrity. The assignments for design example on Intel Agilex® 7 SoC FPGA I-Series development kit must be set as below:

set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=35" -to <tx_serial_pin_name>

set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to <tx_serial_pin_name>

set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to <tx_serial_pin_name>

set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to <tx_serial_pin_name>

set_instance_assignment -name HSSI_PARAMETER "tx_pll_bw_sel=TX_PLL_BW_SEL_MEDIUM" -to <tx_serial_pin_name>