SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/04/2022
Public

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7.1.3.5. Dynamic Reconfiguration

In order to implement dynamic reconfiguration in F-tile device, you will need to use F-tile Dynamic Reconfiguration Suite IP in IP catalog. For more details on the IP, refer to F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide.

To work with this IP, you can create a F-tile PMA/FEC Direct PHY Intel® FPGA IP for each of the data rate you want to support. The PMA/FEC Direct PHY GA IP has no reconfiguration profiles instantiation, and hence multiple instances of this IP are required to support different data rates. For instance, a triple-rate SDI which supports 3 different data rates – 270 Mbps (SD-SDI), 1.485 Gbps (HD-SDI) and 2.97 Gbps (3G-SDI), supposedly requires 3 PHY instances with 3 different data rate configurations. However, since 3G-SDI and SD-SDI can share the same PHY configuration in SDI II Intel® FPGA IP’s transceiver handling, only 2 Direct PHY IP instances are required on RX side. For the TX side, only 1 Direct PHY IP instance is required as the IP does not require reconfiguration between data rates, because the IP is doing oversampling. Refer to Chapter TX Sample. However, if your design requires two reference clocks switching for NTSC and PAL rates, another TX PHY instance is required to connect the TX PLL reference clock to another clock port.

After instantiating these instances, which act as a profile instance, you must connect the link clock port and the serial data interface ports of those instances. Also, the following assignments must be included in the project’s .qsf file to define the reconfiguration group.

set_global_assignment -name IP_RECONFIG_GROUP_TYPE "<your reconfig group name>:EXCLUSIVE:SHARED_SIP:CLK_MASTER"

set_instance_assignment -name IP_RECONFIG_GROUP <your reconfig group name> -to <your main phy instance hierarchy>

set_instance_assignment -name IP_RECONFIG_GROUP <your reconfig group name> -to < your 2nd profile phy instance hierarchy>

set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE ON -to <your main phy instance hierarchy>

set_instance_assignment -name IP_RECONFIG_GROUP_SHARED_SIP ON -to <your main phy instance hierarchy>

set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL PLD_PCS_RX_CLK_OUT1_DCM -to <your main rx aib hierarchy>

set_instance_assignment -name IP_RECONFIG_ID <profile ID> -to <your main phy instance hierarchy>

set_instance_assignment -name IP_RECONFIG_ID <profile ID> -to <your 2nd profile phy instance hierarchy>

set_instance_assignment -name IP_COLOCATE F_TILE -from <DR IP hierarchy> -to <your main phy instance hierarchy>

set_instance_assignment -name IP_COLOCATE F_TILE -from <DR IP hierarchy> -to <your 2nd profile phy instance hierarchy>

SDI II Intel® FPGA IP’s design example includes these assignments in a tcl file for convenient tcl scripting when multiple reconfiguration groups are required for multiple SDI II instances. The design example also contains RTL modules of the reconfiguration controller, as well as an arbiter to interact between SDI II IP and the Dynamic Reconfiguration Suite IP. For more details on the tcl script and RTL example, refer to F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide.

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