SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/04/2022
Public

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7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

The SDI II IP core must to be paired with HSSI channels. For certain Intel® Arria® 10 and Intel® Cyclone® 10 GX device parts, all the HSSI channels reside at one side of the chip. Multiple instantiations of the SDI II IP core in a design (especially for multi-rate mode) may cause that side of the chip to be congested with the ALMs and core logic.
Figure 39. Chip Planner View of HSSI Channels Placement on an Intel® Arria® 10 Device

The architecture for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices is designed to place most HSSI clocks on the peripheral clocks (PCLKs). The logic of the IP core may not fit efficiently into the available regions covered by the PCLKs, and moving the logic farther away is not ideal because the logic needs to interact with the HSSI channels. These circumstances may cause routing challenge and Fitter failure.

To overcome this issue, check the placement of the HSSI channels on the chip and consider the availability of the resources on that side before starting your design.

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