18.104.22.168. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
The architecture for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices is designed to place most HSSI clocks on the peripheral clocks (PCLKs). The logic of the IP core may not fit efficiently into the available regions covered by the PCLKs, and moving the logic farther away is not ideal because the logic needs to interact with the HSSI channels. These circumstances may cause routing challenge and Fitter failure.
To overcome this issue, check the placement of the HSSI channels on the chip and consider the availability of the resources on that side before starting your design.